MIC74(2000) 查看數據表（PDF） - Micrel

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MIC74
(Rev.:2000)

2-Wire Serial I/O Expander and Fan Controller

Micrel 

MIC74

Micrel

P0*

/ALERT

Master-to-slave transmission

Slave-to-master response

P0*

/ALERT

R/W = READ

NOT ACKNOWLEDGE

ACKNOWLEDGE

STOP

S 0 0 0 1 1 0 0 1 A 0 1 0 0 A2 A1 A0 0 /A P

Alert Response Address

(master requests address

of interupting device)

Slave Address

(interrupting MIC74

announces its address)

t/INT

t/IR

* Assumes P0 interrupts properly configured and

enabled. P0 used as an example. Timing for P1

to P7 is identical.

Figure 7. Interrupt Handling Using the Alert Response Address

Master-to-slave transmission

Slave-to-master response

R/W = WRITE

ACKNOWLEDGE

ACKNOWLEDGE

R/W = READ

NOT ACKNOWLEDGE

ACKNOWLEDGE

STOP

S 0 0 0 1 A2 A1 A0 0 A 0 0 0 0 0 0 1 1 A S 0 0 0 1 A2 A1 A0 1 A X X X X X X X X /A P

Slave Address

Command Byte

(host addresses an MIC74) (03h = selects status register)

Slave Address

(host addresses an MIC74)

Status Value†

(MIC74 sends status)

t/INT

t/R

* Assumes P0 interrupts properly configured and

enabled. P0 used as an example. Timing for P1

to P7 is identical.

† STATUS register is cleared to zero following this

operation.

Figure 8. Interrupt Handling Without the Alert Response Address

August 1, 2000

11

MIC74

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