MK50H28 查看數據表（PDF） - STMicroelectronics

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MK50H28

MULTI LOGICAL LINK FRAME RELAY CONTROLLER

STMicroelectronics 

MK50H28

BIT

05

04:03

02

01

00

NAME

BSWPC

DESCRIPTION

This bit determines the byte ordering of all ”non-data” DMA transfers. This transfers

refers to any DMA transfers that access memory other than the data buffers themselves.

This includes the Initialization Block, Descriptors, and Status Buffer. It has no effect on

data DMAtransfers. BSWPC allows the MK50H28 to operate with memory organizations

that have bits 07:00 at even addresses and with bits 15:08 at odd addressses or vice

versa. BSWPC is Read/Write and cleared by BUS RESET.

With BSWPC = 0:

Address

Address

XX0 0 . . . 7

XX1 8 . . . 15

With BSWPC = 1:

Address

XX0 8 . . . 15

Address

XX1 0 . . . 7

BURST

BSWPD

ACON

BCON

This field determines the maximum number of data transfers performed each time control

of the host bus is obtained. BURST is READ/WRITE and cleared on bus Reset.

BURST <1:0>

00

10*

01

8 bit mode

2

16

unlimited

16 bit mode

1

8

unlimited

*Suggested setting

This bit determines the byte ordering of all data DMA transfers. Data transfers are

those to or from a data buffer. BSWPD has no effect on non-data transfers. The effect

of BSWPD on data transfers is the same as that of BSWPC on non-data transfers

(see above). For most applications, including most 68000 based systems, this bit

should be set.

ALE CONTROL defines the assertive state of pin 18 when the MK50H28 is a Bus

Master. ACON is READ/ WRITE and cleared by Bus RESET.

ACON

0

1

PIN18

ASSERTED HIGH

ASSERTED LOW

NAME

ALE

AS

BYTE CONTROL redefines the Byte Mask and Hold I/O pins. BCON is READ/WRITE

and cleared by Bus RESET.

BCON

0

1

PIN16

BM1

B USAK O

PIN15

BM0

BYTE

PIN17

HOLD

BUSRQ

25/64

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