MK50H28 查看數據表（PDF） - STMicroelectronics

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MK50H28

MULTI LOGICAL LINK FRAME RELAY CONTROLLER

STMicroelectronics 

MK50H28

4.2 Initialization / Priority DLCI Block

MK50H28 initialization includes the reading of the Initialization Block in the off-chip memory to obtain the

operating parameters. The Initialization Block is defined below. Upon receiving an Init primitive, the first

16 words of the Initialization block are read by the MK50H28. The remainder of the Initialization block

will be read as needed by the MK50H28. Memory at IADR+32 - IADR+38 should always be initialized

with 0’s prior to issuing the Init Primitive. Any changes to IADR+00 - IADR+31 after initialization require

that the device be stopped and Init primitive be issued again in order to take effect. It is not necessary

that the device be re-initialized after changes to bits in the CSRs (Control and Status Registers).

Figure 8: Initialization / Priority DLCI Block

BASE ADDRESS

HIGHER ADDR

MODE

RESERVED

Ntwk N393 Ntwk N392 User N393 User N392

/ nN3

/ nN2

Counter dN1 (Max Frame Length)

Counter nN1/N391 SCALER

Timer nT1 / T391

Timer nT2 / T392

Timer TP

RESERVED CTADR <23:16>

CTADR <15:00>

RESERVED ALTADR <23:16>

ALTADR <15:00>

RESERVED TINTADR<23:16>

TINTADR <23:16>

RESERVED RINTADR<23:16>

RINTADR <23:16>

RESERVED-Must be written with 0’s

Counter nN1

(If EIBEN=1)

SBA <15:00>

SBA <15:00>

ERROR COUNTERS

and STATISTICS

RESERVED

PRIORITY DLCI

BLOCK

(256 Entries Maximum)

IADR+00

IADR+02

IADR+04

IADR+06

IADR+08

IADR+10

IADR+12

IADR+14

IADR+16

IADR+18

IADR+20

IADR+22

IADR+24

IADR+28

IADR+32-38

IADR+40

IADR+42

IADR+44

THRU

IADR+89

IADR+96

THRU

IADR+XX

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