ML7204-001 查看數據表（PDF） - Oki Electric Industry
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ML7204-001 Datasheet PDF : 42 Pages
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OKI Semiconductor
FEDL7204-001DIGEST-01
ML7204-001
ABSOLUTE MAXIMUM RATINGS
Parameter
Analog power supply
voltage
Digital power supply
voltage
Analog input voltage
Digital input voltage
Output current
Power dissipation
Storage temperature
Symbol
AVDD
Condition
—
Rating
Unit
–0.3 to +4.6
V
DVDD
—
–0.3 to +4.6
V
VAIN
Analog pin
–0.3 to AVDD+0.3
V
VDIN1
Normal digital pin
–0.3 to DVDD+0.3
V
VDIN2 5 V tolerant pin DVDD = 3.0 to 3.6 V
–0.3 to +6.0
V
DVDD < 3.0 V
–0.3 to DVDD+0.3
V
IO
—
–20 to +20
mA
PD
Ta = 60 °C, per package
350
mW
Tstg
—
–65 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Analog power supply voltage
Digital power supply voltage
Operating temperature range
Digital high-level input voltage
Digital low-level input voltage
Digital input rise time
Digital input fall time
Digital output load capacitance
Digital output load resistance
AVREF bypass capacitor
VREGOUT bypass capacitor
VBG bypass capacitor
Master clock frequency
PCM shift clock frequency
PCM synchronous signal
frequency
Clock duty ratio
PCM synchronous timing
PCM synchronous signal width
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60°C unless otherwise specified)
Symbol
Condition
Min. Typ. Max. Unit
AVDD
—
3.0
3.3
3.6
V
DVDD
—
3.0
3.3
3.6
V
Ta
—
–20
—
60
°C
VIH1
Normal digital pin
0.75 ×
DVDD
—
DVDD+
0.3
V
VIH2
5 V tolerant pin
0.75 ×
DVDD
—
5.5
V
VIL
Digital pin
–0.3
—
0.19 ×
DVDD
V
tIR
Digital pin
—
2
20
ns
tIF
Digital pin
—
2
20
ns
CDL
Digital pin
—
—
50
pF
RDL Pull-up resistance, PCMO 500
—
—
Ω
Cvref Between AVREF-AGND 2.2+0.1 — 4.7+0.1 µF
Cvout Between VREGOUT-DGND — 10+0.1 —
µF
CVBG
Between VBG-DGND
—
150
—
pF
Fmck
MCK
–0.01% 12.288 +0.01% MHz
Fbclk
BCLK (at input)
64
—
2048 kHz
Fsync
SYNC (at input)
—
8.0
—
kHz
DRCLK MCK, BCLK (at input)
40
50
60
%
tBS BCLK to SYNC (at input) 100
—
—
ns
tSB SYNC to BCLK (at input) 100
—
—
ns
tWS
SYNC (at input)
1BCLK —
100
µs
(Note) On power-on/shut-down sequence
For the analog power supply voltage (AVDD) and the digital power supply voltage (DVDD) to be supplied to
this LSI, it is recommended that power be applied to them simultaneously. However, if simultaneous power-up
is difficult due to the power supply circuit configuration, power them up in the order of DVDD → AVDD.
The power supplies should be shut down in the reverse order of power-on sequence.
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