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MMDF2N06V1 Datasheet PDF : 4 Pages
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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TMOS V™
SO-8 for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resis-
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
G
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
• Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETS
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET
• Miniature SO–8 Surface Mount Package – Saves Board Space
• Mounting Information for SO–8 Package Provided
TM
D
S
MMDF2N06V
DUAL TMOS MOSFET
3.3 AMPERES
60 VOLTS
RDS(on) = 0.115 OHM
CASE 751–05, Style 11
SO–8
Source–1
Gate–1
Source–2
Gate–2
18
27
36
45
Top View
Drain–1
Drain–1
Drain–2
Drain–2
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Drain–to–Source Voltage
Drain–to–Gate Voltage, (RGS = 1 MΩ)
Gate–to–Source Voltage — Continuous
Drain Current — Continuous @ TA = 25°C
Drain Current — Continuous @ TA = 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 3.3 Apk, L = 10 mH, RG = 25 Ω)
Thermal Resistance, Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 0.0625″ from case for 10 seconds
VDSS
VDGR
VGS
ID
ID
IDM
PD
TJ, Tstg
EAS
RθJA
TL
DEVICE MARKING
2N06V
(1) Mounted on G10/FR4 glass epoxy board using minimum recommended footprint.
ORDERING INFORMATION
Device
Reel Size
Tape Width
Quantity
MMDF2N06V1
7″
12mm embossed tape
500
MMDF2N06V2
13″
12mm embossed tape
2500
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Value
60
60
± 20
3.3
0.5
9.9
2.0
– 55 to 175
54
62.5
260
Unit
Vdc
Vdc
Vdc
Adc
Apk
W
°C
mJ
°C/W
°C
©MMoottoororolal,aInTc.M19O9S6 Power MOSFET Transistor Device Data
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