MP7613 查看數據表（PDF） - Exar Corporation
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MP7613 Datasheet PDF : 16 Pages
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MP7613
A standard µ-processor and TTL/CMOS compatible input
data port loads the data into the pre-selected DACS. If CS = 0,
the chip accesses digital data on the bus. Then address bits A0
to A2 select the appropriate DAC and LD1 loads the data into the
first-latch-bank. When all 8-channels first-latch-banks are
loaded, then LD2 enables the second-latch-bank and updates
all 8-channels simultaneously. The selected DAC becomes
transparent (activity on the digital inputs appear at the analog
output) when both LD1 = LD2 = 0.
R1 = 0 resets the first-latch-bank. R2 = 0 resets the second-
latch-bank which sets the analog output to zero volts (data =
100...00), regardless of digital inputs.
Function
Load Latch 1 of DAC1
Load Latch 1 of DAC2
Load Latch 1 of DAC3
Load Latch 1 of DAC4
Load Latch 1 of DAC5
Load Latch 1 of DAC6
Load Latch 1 of DAC7
Load Latch 1 of DAC8
A2 A1 A0 RD LD1 LD2 CS R1 R2
0
0
0
1 0→1 1
0
1
1
0
0
1
1 0→1 1
0
1
1
0
1
0
1 0→1 1
0
1
1
0
1
1
1 0→1 1
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
0→1 1
0→1
0→1
0→1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
Load Latch 2 of DAC1→8 X
X
X
1
1 0→1 0
1
1
Read Latch 1 of DAC1
Read Latch 1 of DAC2
Read Latch 1 of DAC3
Read Latch 1 of DAC4
Read Latch 1 of DAC5
Read Latch 1 of DAC6
Read Latch 1 of DAC7
Read Latch 1 of DAC8
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
Reset Latch 1 of DAC1→8 X
X
X
X
X
X
X
0
1
Reset Latch 2 of DAC1→8 X
X
X
X
X
X
X
1
0
Note: 1: High, 0: Low, X: Don’t Care
Table 1. Octal Parallel Data Input 14-Bit DAC Truth Table
Note: For timing information see Electrical Characteristics
Rev. 2.00
A0 to A2 3
3-8
8
Decoder
8
To first latch bank enable
LD1
8
CS
8
To switches across the first latch
bank for readback enable
RD
LD2
To second latch bank enable
R1
To reset all first latch bank
R2
To reset all second latch bank
Figure 4. Simplified Parallel Logic Port
8
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