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MP8798AN 查看數據表(PDF) - Exar Corporation

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MP8798AN Datasheet PDF : 20 Pages
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MP8798
ELECTRICAL CHARACTERISTICS TABLE (CONT’D)
Parameter
25°C
Symbol
Min
Typ
Max
Units Test Conditions/Comments
DIGITAL OUTPUTS
COUT=15 pF
Logical “1” Voltage
VOH DVDD-0.5
V
ILOAD = 2 mA
Logical “0” Voltage
VOL
0.4
V
ILOAD = 4 mA
Tristate Leakage
IOZ
0
5
µA
VOUT = 0 to DVDD
Data Hold Time (See NO TAG)1
tHLD
30
35
ns
Data Valid Delay1
tDL
35
45
ns
Write Pulse Width1
tWR
40
ns
Multiplexer Address Setup Time1
tAS
80
ns
Multiplexer Address Hold Time1
tAH
0
ns
Delay from WR to Multiplexer1
Enable
Power Down Time1
Power Up Time1
tMUXEN1
tPD
tPU
80
ns
300
ns
200
ns
POWER SUPPLIES8
Power Down (IDD)
IPD-DD
0.6
Operating Voltage (AVDD, DVDD)
VDD
4
5
Current (AVDD + DVDD)
IDD
6
1.2
mA
6.5
V
10
mA
VIN = 2 V
NOTES:
1 Guaranteed. Not tested.
2 Tester measures code transition voltages by dithering the voltage of the analog input (VIN). The difference between the measured
code width and the ideal value (VREF/1024) is the DNL error (see NO TAG). The INL error is the maximum distance (in LSBs) from
the best fit line to any transition voltage (See Figure 7.).
3 See VIN input equivalent circuit (see Figure 9.).
4 Clock specification to meet aperture specification (tAP). Actual rise/fall time can be less stringent with no loss of accuracy.
5 Specified values guarantee functional device. Refer to other parameters for accuracy.
6 System can clock MP8798 with any duty cycle as long as all timing conditions are met.
7 Input range where input is converted correctly into binary code. Input voltage outside specified range converts to zero or full scale
output.
8 DVDD and AVDD are connected through the silicon substrate. Connect together at the package.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2
VDD (to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
VREF(+) & VREF(–) . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V
All Inputs . . . . . . . . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V
All Outputs . . . . . . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V
Storage Temperature . . . . . . . . . . . . . . . . . . . –65 to +150°C
Lead Temperature (Soldering 10 seconds) . . . . . . . +300°C
Package Power Dissipation Rating to 75°C
SOIC, PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000mW
Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 14mW/°C
NOTES:
1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short
transients outside the supplies of less than 100mA for less than 100µs.
3 VDD refers to AVDD and DVDD. GND refers to AGND and DGND.
Rev. 3.00
5

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