MP8830AE 查看數據表（PDF） - Exar Corporation

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MP8830AE

Triple 10-bit High Speed Analog-to-Digital Converter with Digitally Controlled References

Exar Corporation 

MP8830

CDC

AIN

ACLP

+ AAN

–

Gain

DAC 9

ADC

DT/H CMP

Logic

10

Offset

DAC 6

Channel A of MP8830

Figure 5. Simplified Diagram

Channel A Example

Black Level Switch Operation

The MP8830 is equipped with a black level setting switch.

The function of the black level setting switch is to store the DC

offset value of the ADC as well as the common mode value of

AIN across the external CDC-hold capacitor. This is a cost effec-

tive method to store the black level of AIN or the offset of the sys-

tem. Note that the ACLP, BCLP, and CCLP level is DC shifted to

accommodate for the distribution of ADC offset.

One terminal of each clamp switch is connected at the ladder

tap voltage which corresponds to +4 LSB from the ADC

000(hex) to 001(hex) transition. This 4 LSB offset allows the

ADC to measure as low as –4 LSB of the analog input voltage

relative to the clamp voltage. To increase the negative input de-

tectable range, clamp with the offset DAC at a code higher than

00(hex).

The second terminal of the clamp switch is connected to a pin

with its corresponding channel prefix. For channel A, the pin is

named ACLP.

The control of the all the switches is provided by a separate

unlatched logic input called DCL. The delay from DCL falling

edge to switch on is specified as t16. The actual time required to

store the bias voltage depends on the external C value, and bias

variation from sample to sample. The equivalent impedance of

the clamp is 100Ω typical, spec name of RON, and must be in-

cluded in the analysis of the zero sample time considerations.

The black level is a function of the offset DAC, and therefore

requires that the value of the offset DAC be loaded into the offset

DAC second register before the clamp is turned on. This value

can be set from 00(hex) to 3F(hex) corresponding to a clamp

level change of ZSR.

The voltage swing at the ACLP, BCLP, CCLP pin after clamp

should be limited to the range of AVDD to AGND. This will pre-

vent the stored charge on the holding cap from being changed

by the input protection devices.

A 50Ω to 100Ω resistor in series with the ACLP, BCLP, CCLP

pin will limit the current induced in the protection and parasitic

diodes due to over-voltages induced by the source. Limit this

current with the use of external protection diodes.

MSB=1

9 First

Gain

Register

9

m

Decoder

m

2nd

Register

m

Gain DAC

Control

Data

VREF Gain

DAC

R

R

–

+

R

R

VRT

RLAD

10 To

10-Bit

ADC

6 First n

Offset

Register

n

Decoder

n

2nd

Register

n

DAC

R

R

VRB

–

Offset

DAC

Control

Data

VREF Offset

+

R

R

Rev. 1.00

Figure 6. MP8830 Single-Channel Equivalent Circuit

11

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