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¡ Semiconductor
Serial Output Timing
MSM7602
fSCK, tSCK
tDSC
SCK
tXS
tSX
tCYC
SYNC
tWSY
tSD
tXD
tXD
tXD
, SOUT High-Z MSB
LSB High-Z
ROUT
7
6
5
4
3
2
1
0
Operation Timing After Reset
tWR
RST
*Reset timing can be asynchronous
tDIT
MSB
7
tDRS
tDRE
Internal operaion
Reset
Initialization
Processing Start
Power Down Timing
PWDWN
tDPS
Internal Operation
Note: INT is invalid in the diagonally shaded interval.
Power Down
tDPE
Processing Start
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