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MSM7602-011 查看數據表(PDF) - Oki Electric Industry

零件编号
产品描述 (功能)
比赛名单
MSM7602-011
OKI
Oki Electric Industry OKI
MSM7602-011 Datasheet PDF : 29 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
¡ Semiconductor
MSM7602
(4/5)
Pin
28-pin 56-pin
SSOP QFP
20 34
22 36
23 37
24 38
25 39
26 40
Symbol
PWDWN
SYNCO
SCKO
RST
WDT
GC
Type
Description
I Power-down mode control when powered down.
"L": Power-down mode
"H": Normal operation mode
During power-down mode, all input pins are disabled and output pins are
in the following states :
High impedance : SOUT, ROUT, PD0 to 15
"L": SYNCO, SCKO, MCKO
"H": OF1, OF2, X2
Holds the last state : WDT, IRLD
Reset after the power-down mode is released.
O 8 kHz sync signal for the PCM CODEC.
Connect to the SYNC pin and the PCM CODEC transmit/receive sync pin.
Leave it open if using an external SYNC.
O Transmit clock signal (256 kHz) for the PCM CODEC.
Connect to the SCK pin and the PCM CODEC transmit/receive clock pin.
Leave it open if using an external SCK.
I Reset signal.
"L": Reset mode
"H": Normal operation mode
Due to initialization, input signals are disabled for 100 ms after reset
(after RST is returned from L to H).
Input the basic clock during the reset.
Output pins during the reset are in the following states :
High impedance: SOUT, ROUT, PD0 to 15
"L": WDT
"H": OF1, OF2
Not affected: X2, SYNCO, SCKO, IRLD, MCKO
O Test program end signal.
This signal is output when the one cycle (8kHz) of processing is completed.
Leave it open.
I Input signal by which the gain controller for the RIN input is
controlled and the RIN input level is controlled and howling is
prevented.
The gain controller adjusts the RIN input level when it is –20 dBm0 or
above. RIN input levels from –20 to –11.5 dBm0 will be suppressed to
–20 dBm0 in the attenuation range from 0 to 8.5 dB.
RIN input levels above –11.5 dBm0 will always be attenuated by 8.5 dB.
• Single Chip or Master Chip in a Cascade Connection
"H": Gain control ON
"L": Gain control OFF
"H" is recommended for echo cancellation.
• Slave Chip in a Cascade Connection
Fixed at "L"
This pin is loaded in synchronization with the falling edge of the INT signal
or the rising edge of RST.
8/29

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