MSM7716PMB 查看數據表（PDF） - Oki Electric Industry

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MSM7716PMB

Single Rail Linear CODEC

Oki Electric Industry 

OKI Semiconductor

FEDL7716P-01

MSM7716P

PCMOUT

PCM signal output.

The PCM output signal is output from MSD in sequential order, synchronously with the rising edge of the BCLK

signal.

MSD may be output at the rising edge of the SYNC signal, depending on the timing between BCLK and SYNC.

This pin is in high impedance state except during 14-bit PCM output, and is in either in high impedance or in “L”

output state during power down and power saving mode.

A pull-up resistor must be connected to this pin, because its output is configured as an open drain.

The output coding format is in 14-bit 2’s complement.

The MSD represents a polarity of the signal with respect to the signal ground.

Table 1

Input/Output Level

+Full scale

+1

0

–1

–Full scale

MSD

0111

0000

0000

1111

1000

PCMIN/PCMOUT

1111

0000

0000

1111

0000

1111

0000

0000

1111

0000

11

01

00

11

00

PDN

Power down control signal input.

A digital “L” level drives both transmit and receive circuits to a power down state.

The control registers are set to the initial state.

Be sure to initialize the control registers by to execute this power down by keeping this pin to digital '0' level for

100 ns or longer after the power is turned on the power and the VDD exceeds 3.0 V.

SGC

Connection of a bypass capacitor for generating the signal ground voltage level.

Connect a 0.1 µF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin.

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