MSM7718-01 查看數據表（PDF） - Oki Electric Industry

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MSM7718-01

Echo Canceler with ADPCM CODEC

Oki Electric Industry 

¡ Semiconductor

MSM7718-01

MCKSL

Master clock selection input.

Set MCKSL to logic “0” when the master clock frequency is 9.6 MHz, and to logic “1” when it is 19.2

MHz.

PCMPCO

PCM data output of the PCM CODEC.

PCM is output from MSB, synchronizing with the rising edge of BCLKP and SYNCP. This pin is in

a high impedance state except during 8-bit PCM output. (It is also in a high impedance state during

power-down mode.) A pull-up resistor must be connected to this pin because its output is configured

as an open drain.

PCMPCI

PCM data input of the PCM CODEC.

PCM is shifted in at the falling edge of the BCLKP signal. The start of the PCM data (MSB) is

identified at the rising edge of SYNCP.

PCMADO

PCM data output of the ADPCM transcoder.

PCM is the output data after ADPCM decoder processing and is serially output from MSB in

synchronization with the rising edge of BCLKP and SYNCP. However, this signal timing can be

controlled at PCM multiplexing by the control register CR1-B5.

(The time slot 1 or 2 can be selected. Refer to Figs. 2-4.)

This pin is in a high impedance state except during 8-bit PCM output. (It is also in an high impedance

state during power-down mode.) A pull-up resistor must be connected to this pin because its output

is configured as an open drain.

PCMADI

PCM data input of the ADPCM transcoder.

PCM is shifted in at a falling edge of the BCLKP signal and input from MSB. The start of the PCM

data (MSB) is identified at the rising edge of SYNCP. However, this signal timing can be controlled at PCM

multiplexing by the control register CR1-B5.

(The time slot 1 or 2 can be selected. Refer to Figs. 2-4.)

PCMLNO

PCM receive data output of the line echo canceler.

PCM is output from MSB in a sequential order, synchronizing with the rising edge of BCLKP and

SYNCP. However, this signal timing can be controlled at PCM multiplexing by the control

register CR2-B3 to B5.

(The time slot of 1 to 7 can be selected. Refer to Figs. 2-4.)

This pin is in a high impedance state except during 8-bit PCM output. (It is also in a high impedance

state during power-down mode.) A pull-up resistor must be connected to this pin because its output

is configured as an open drain.

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