M48T18-100PC 查看數據表（PDF） - STMicroelectronics

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M48T18-100PC

CMOS 8K x 8 TIMEKEEPER SRAM

STMicroelectronics 

M48T08, M48T18

DESCRIPTION (cont’d)

24 hour BCD format. Corrections for 28, 29 (leap

year), 30, and 31 day months are made automat-

ically. Byte 1FF8h is the clock control register. This

byte controls user access to the clock information

and also stores the clock calibration setting.

The eight clock bytes are not the actual clock

counters themselves; they are memory locations

consisting of BiPORT™ read/write memory cells.

The M48T08,18 includes a clock control circuit

which updates the clock bytes with current informa-

tion once per second. The information can be

accessed by the user in the same manner as any

other location in the static memory array.

The M48T08,18 also has its own Power-fail Detect

circuit. The control circuitry constantly monitors the

single 5V supply for an out of tolerance condition.

When VCC is out of tolerance, the circuit write

protects the SRAM, providing a high degree of data

security in the midst of unpredictable system opera-

tion brought on by low VCC. As VCC falls below

approximately 3V, the control circuitry connects the

battery which maintains data and clock operation

until valid power returns.

READ MODE

The M48T08,18 is in the Read Mode whenever W

(Write Enable) is high, E1 (Chip Enable 1) is low,

and E2 (Chip Enable 2) is high. The device archi-

tecture allows ripple- through access of data from

eight of 65,536 locations in the static storage array.

Thus, the unique address specified by the 13 Ad-

dress Inputs defines which one of the 8,192 bytes

of data is to be accessed. Valid data will be avail-

able at the Data I/O pins within tAVQV (Address

Access Time) after the last address input signal is

stable, providing that the E1, E2, and G access

times are also satisfied. If the E1, E2 and G access

times are not met, valid data will be available after

the latter of the Chip Enable Access Times (tE1LQV

or tE2HQV) or Output Enable Access Time (tGLQV).

The state of the eight three-state Data I/O signals

is controlled by E1, E2 and G. If the outputs are

activated before tAVQV, the data lines will be driven

to an indeterminate state until tAVQV. If the Address

Inputs are changed while E1, E2 and G remain

active, output data will remain valid for tAXQX (Out-

put Data Hold Time) but will go indeterminate until

the next Address Access.

WRITE MODE

The M48T08,18 is in the Write Mode whenever W,

E1, and E2 are active. The start of a write is refer-

enced from the latter occurring falling edge of W or

E1, or the rising edge of E2. A write is terminated

by the earlier rising edge of W or E1, or the falling

edge of E2. The addresses must be held valid

throughout the cycle. E1 or W must return high or

E2 low for minimum of tE1HAX or tE2LAX from Chip

Enable or tWHAX from Write Enable prior to the

initiation of another read or write cycle. Data-in

must be valid tDVWH prior to the end of write and

remain valid for tWHDX afterward. G should be kept

high during write cycles to avoid bus contention;

although, if the output bus has been activated by a

low on E1 and G and a high on E2, a low on W will

disable the outputs tWLQZ after W falls.

DATA RETENTION MODE

With valid VCC applied, the M48T08,18 operates as

a conventional BYTEWIDE static RAM. Should the

supply voltage decay, the RAM will automatically

power-fail deselect, write protecting itself when VCC

falls within the VPFD(max), VPFD(min) window. All

outputs become high impedance, and all inputs are

treated as ”don’t care.”

Note: A power failure during a write cycle may

corrupt data at the currentlyaddressed location, but

does not jeopardize the rest of the RAM’s content.

At voltages below VPFD(min), the user can be as-

sured the memory will be in a write protected state,

provided the VCC fall time is not less than tF. The

M48T08,18 may respond to transient noise spikes

on VCC that reach into the deselect window during

the time the device is sampling VCC. Therefore,

decoupling of the power supply lines is recom-

mended.

When VCC drops below VSO, the control circuit

switches power to the internal battery which pre-

serves data and powers the clock. The internal

button cell will maintain data in the M48T08,18 for

an accumulated period of at least 10 years when

VCC is less than VSO. As system power returns and

VCC rises above VSO, the battery is disconnected,

and the power supply is switched to external VCC.

Write protection continues until VCC reaches

VPFD(min). E1 should be kept high or E2 low as

VCC rises past VPFD(min) to prevent inadvertent

write cycles prior to processor stabilization. Normal

RAM operationcan resume tREC after VCC exceeds

VPFD(max).

POWER FAIL INTERRUPT PIN

The M48T08,18 continuously monitors VCC. When

VCC falls to the power-fail detect trip point, an

interrupt is immediately generated. An internal

clock provides a delay of between 10µs and 40µs

before automatically deselecting the M48T08,18.

The INT pin is an open drain output and requires

an external pull up resistor, even if the interrupt

output function is not being used.

9/18

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