MT8920 查看數據表（PDF） - Mitel Networks

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MT8920

ISO-CMOS ST-BUS™ FAMILY ST-BUS Parallel Access Circuit

Mitel Networks 

CMOS MT8920B

AC Electrical Characteristics†- Mode 1 Parallel Bus Timing (see Fig. 14)

(VCC=5.0V ±5%,TA=-40 to 85°C)

Characteristics

Sym Min Typ‡ Max Units

Test Conditions

1 Address to DS (CS) Low††

2 R/W to DS (CS) Low††

3 DS (CS) Low to DTACK Low††

tARDS

0

ns

tRWDS 20

ns

tRDS1,2 tcwm tCLK 2*tCLK

ns

Load C

4 Valid Data to DTACK Low (Read)

tRD

tcwm

-30

ns

Load A, CL=130pF, RL=740Ω

5 DS High to DTACK High

tDAR

65

ns Load C, CL=50pF

6 DS High to Data High Imped.(Read) tDHZ

0

45

ns

Load A, CL=130pF, RL=740Ω

7 DS High to CS High

tCSH

0

ns

8 Data Hold Time (Write)

tDHT

0

ns

9 Input Data Valid after DS

tDST

tcwm

ns

-30

10 Address Hold Time††

tADHT 50

ns

† Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25°C, VDD=5V, tCLK=244 ns, tCH=tCL=122 ns and are for design aid only: not guaranteed and not subject to production

testing.

††The cycle is initiated by the falling edge of CS or DS, whichever occurs last. Timing is relative to the last falling edge which initiates the cycle.

(1) tcwm is equal to tCH or tCL whichever is smaller (some ST-BUS compatible transceivers may generate C4 clock having tCHmin=70ns

or tCLmin=70ns.

(2) Worst case access when memory contention occurs.

A0 - A5

CS (IACK†)

R/W

tADHT

tARDS

tRWDS

DS

tRDS

DTACK

D0 - D7

tRD

DATA OUT

tDST

tDHT

D0 - D7

DATA IN

Figure 14 - Mode 1 Parallel Bus Timing

† During Interrupt Acknowledge cycle IACK replaces CS. R/W must remain high.

tCSH

tDAR

tDHZ

3-19

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