MT9075 查看數據表（PDF） - Mitel Networks

零件编号

产品描述 (功能)

比赛名单

MT9075

E1 Single Chip Transceiver

Mitel Networks 

MT9075A

Preliminary Information

Pin Description (continued)

Pin #

PLCC MQFP

Name

Description

64 61 TxDLCLK Transmit Data Link Clock (Output). A gapped clock signal derived from a gated 2.048

Mbit/s clock for transmit data link at 4, 8, 12, 16 or 20 kHz. The transmit data link data

(TxDL) is clocked in on the rising edge of TxDLCLK. TxDLCLK can also be used to clock

DL data out of an external serial controller.

65 62

TxDL

Transmit Data Link (Input). An input serial stream of transmit data link data at 4, 8, 12,

16 or 20 kbit/s composed of 488ns-wide bit cells which are multiplexed into selected

national bits of the PCM 30 transmit signal.

66 63

BL/FR BusorLine/Freerun (Input). If this pin is set to high, the MT9075A is in the System Bus

or Line Synchronous mode depending on the BS/LS pin. If low, the MT9075A is in the

free run mode.

67 64 VDD Positive Power Supply (Input). Digital supply (+5V ± 5%).

68 65 VSS Negative Power Supply (Input). Digital ground.

1-7,

NC No Connection. Leave open for normal operation.

25-31,

49-56,

75-82,

100

4-134

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