MT9075B 查看數據表（PDF） - Zarlink Semiconductor Inc

零件编号

产品描述 (功能)

生产厂家

MT9075B

E1 Single Chip Transceiver

Zarlink Semiconductor Inc 

MT9075B

Data Sheet

dB

0.5

0

-20 dB/decade

-19.5

10

40

400

10K

Figure 8 - Typical Jitter Attenuation Curve

Mode Name

BS/LS BL/FR JAS JAT/JAR

Note

SysBusSync1

1

1

1

1

JA on Tx side; No JA on Rx side

SysBusSync2

1

1

1

0

JA on Rx side; No JA on Tx side

SysBusSync3

1

1

0

x

No JA on Tx or Rx side

Line

0

Synchronous

1

x

x

By default, JA is on the receive side.

Controls bits need not be selected.

Free-Run

x

0

x

x

In free-run mode JA will be automatically

disconnected

Table 2 - Selection of Clock Jitter Attenuation Modes

Depending on the mode selected, the Jitter Attenuator (JA) can attenuate either transmit clock jitter or receive

clock jitter, or be disconnected. Control bits JAS, JAT/JAR (address 18H of page 02H) determine the JA

selection under certain modes. Table 2 shows the configuration of related control pins and control bits required

to place the MT9075B in the appropriate jitter attenuation mode.

Referring to the mode names given in Table 2, theFbreaqsuiecncoyp(eHrza) tion of the jitter attenuation modes is summarized

as follows:

• In SysBusSync (1-3) modes, pins C4b and F0b are always configured as inputs, while in the Line

Synchronous and Free-Run modes C4b and F0b are configured as outputs.

• In SysBusSync1 mode, an external clock is applied to C4b. The applied clock is dejittered by the internal

PLL before being used to transmit data. The clock extracted (with no jitter attenuation performed) from the

receive data can be monitored on pin E2o.

13

Zarlink Semiconductor Inc.

Share Link: