MT9094 查看數據表（PDF） - Mitel Networks

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MT9094

ISO2-CMOS ST-BUS™ FAMILY Digital Telephone (DPhone-II)

Mitel Networks 

MT9094

DSTi

7

DSTo

8

C4i

9

F0i

10

VSSD

11

NC

12

SCLK

13

DATA 2

14

DATA 1

15

CS

16

WD

17

39 SPKR+

38 SPKR-

37 HSPKR+

36 HSPKR-

35 VDD

34 BP

33 S12

32 S11

31 S10

30 S9

29 S8

44 PIN PLCC

Figure 2 - Pin Connections

Pin Description

Pin # Name

Description

1

M+ Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier from the

handset microphone.

2

NC No Connect. No internal connection to this pin.

3

VBias Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers.

Connect 0.1 µF capacitor to VSSA.

4

VRef Reference voltage for codec (Output). Nominally [(VDD/2)-1.5] volts. Used internally.

Connect 0.1 µF capacitor to VSSA.

5

IC Internal Connection. Tie externally to VSS for normal operation.

6 PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low).

7 DSTi ST-BUS Serial Stream (Input). 2048 kbit/s input stream composed of 32 eight bit channels;

the first four of which are used by the MT9094. Input level is TTL compatible.

8 DSTo ST-BUS Serial Stream (Output). 2048 kbit/s output stream composed of 32 eight bit

channels. The MT9094 sources digital signals during the appropriate channel, time coincident

with the channels used for DSTi.

9

C4i 4096 kHz Clock (Input). CMOS level compatible.

10 F0i Frame Pulse (Input). CMOS level compatible. This input is the frame synchronization pulse

for the 2048 kbit/s ST-BUS stream.

11 VSSD Digital Ground. Nominally 0 volts.

12 NC No Connect. No internal connection to this pin.

13 SCLK Serial Port Synchronous Clock (Input). Data clock for MCS-51 compatible microport. TTL

level compatible.

7-46

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