MT9162 查看數據表（PDF） - Mitel Networks
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MT9162 Datasheet PDF : 17 Pages
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Advance Information
MT9162
tR
CLOCKin 70%
(BCL)
30%
70%
Din
30%
Dout
70%
30%
tDOZL
tDOZH
STB
70%
30%
tBCLH
tBCL
tF
tBCLL
tDIS
tDIH
tSSS
tDD
tENW
tSSH
tDOLZ
tDOHZ
NOTE: Levels refer to % VDD (CMOS I/O)
Figure 5 - SSI Synchronous Timing Diagram
AC Electrical Characteristics† - SSI BUS Asynchronous Timing (note 1) (see Figure 6)
Characteristics
Sym
Min
Typ‡
Max Units Test Conditions
1 Bit Cell Period
2 Frame Jitter
3 Bit 1 Dout Delay from STB
going high
4 Bit 2 Dout Delay from STB
going high
5 Bit n Dout Delay from STB
going high
TDATA
Tj
tdda1
tdda2
tddan
600+
TDATA-Tj
600 +
(n-1) x
TDATA-Tj
7812
3906
600
Tj+600
600+
TDATA
600 +
(n-1) x
TDATA
600 +
TDATA+Tj
600 +
(n-1) x
TDATA+Tj
ns BCL=128 kHz
ns BCL=256 kHz
ns
ns CL=150 pF, RL=1K
ns CL=150 pF, RL=1K
ns CL=150 pF, RL=1K
n=3 to 8
6 Bit 1 Data Boundary
TDATA1 TDATA-Tj
TDATA+Tj
ns
7 Din Bit n Data Setup time from tSU
TDATA\2
STB rising
+500ns-Tj
+(n-1) x
TDATA
ns n=1-8
8 Din Data Hold time from STB
tho
TDATA\2
ns
rising
+500ns+Tj
+(n-1) x
TDATA
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
7-171
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