MT9300 查看數據表（PDF） - Mitel Networks

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MT9300

Multi-Channel Voice Echo Canceller

Mitel Networks 

Advance Information

MT9300

Echo Canceller A, Rin Peak Detect Register 2 (RP)

Echo Canceller B, Rin Peak Detect Register 2 (RP)

7

6

5

4

3

2

1

RP15 RP14

RP13

RP12

RP11 RP10

RP9

Read Address: 0Dh + Base Address

Read Address: 2Dh + Base Address

0

Power Reset Value

N/A

RP8

Echo Canceller A, Rin Peak Detect Register 1 (RP)

Echo Canceller B, Rin Peak Detect Register 1 (RP)

7

6

5

4

3

2

1

RP7

RP6

RP5

RP4

RP3

RP2

RP1

Read Address: 0Ch + Base Address

Read Address: 2Ch + Base Address

0

Power Reset Value

N/A

RP0

These peak detector registers allow the user to monitor the receive in signal (Rin) peak signal level. The information is in 16-bit 2’s

complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low

byte is in Register 1.

Echo Canceller A, Sin Peak Detect Register 2 (SP)

Echo Canceller B, Sin Peak Detect Register 2 (SP)

7

6

5

4

3

2

1

SP15

SP14

SP13 SP12

SP11 SP10

SP9

Read Address: 0Fh + Base Address

Read Address: 2Fh + Base Address

0

Power Reset Value

N/A

SP8

Echo Canceller A, Sin Peak Detect Register 1 (SP)

Echo Canceller B, Sin Peak Detect Register 1 (SP)

7

6

5

4

3

2

1

SP7

SP6

SP5

SP4

SP3

SP2

SP1

Read Address: 0Eh + Base Address

Read Address: 2Eh + Base Address

0

Power Reset Value

N/A

SP0

These peak detector registers allow the user to monitor the send in signal (Sin) peak signal level. The information is in 16-bit 2’s

complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low

byte is in Register 1.

Echo Canceller A, Error Peak Detect Register 2 (EP)

Echo Canceller B, Error Peak Detect Register 2 (EP)

7

6

5

4

3

2

1

EP15

EP14

EP13

EP12

EP11 EP10

EP9

Read Address: 11h + Base Address

Read Address: 31h + Base Address

0

Power Reset Value

N/A

EP8

Echo Canceller A, Error Peak Detect Register 1 (EP)

Echo Canceller B, Error Peak Detect Register 1 (EP)

7

6

5

4

3

2

1

EP7

EP6

EP5

EP4

EP3

EP2

EP1

Read Address: 10h + Base Address

Read Address: 30h + Base Address

0

Power Reset Value

N/A

EP0

These peak detector registers allow the user to monitor the error signal peak level. The information is in 16-bit 2’s complement

linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in

Register 1.

17

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