HB54A5129F1-10B(2003) 查看數據表（PDF） - Elpida Memory, Inc

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HB54A5129F1-10B
(Rev.:2003)

512MB Registered DDR SDRAM DIMM

Elpida Memory, Inc 

HB54A5129F1-B75B/10B

Differential Clock Net Wiring (CK0, /CK0)

0ns (nominal)

SDRAM

PLL

stack

CK0

EOL /CK0

OUT1

120Ω

IN

120Ω

OUT'N'

C

Feedback

120Ω

SDRAM

stack

240Ω Register1

(Typically two registers per DIMM)

240Ω Register2

Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl

be set to 0 ns (nominal).

2. Input, output and feedback clock lines are terminated from line to line as shown, and not

from line to ground.

3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired

P in a similar manner.

roduct 4. Termination resistors for feedback path clocks are located after the pins of the PLL.

Data Sheet E0090H60 (Ver. 6.0)

9

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