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V43658Y04VATG-75 查看數據表(PDF) - Mosel Vitelic Corporation

零件编号
产品描述 (功能)
比赛名单
V43658Y04VATG-75
Mosel-Vitelic
Mosel Vitelic Corporation  Mosel-Vitelic
V43658Y04VATG-75 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
MOSEL VITELIC
SPD-Table for -10 PC modules: (Continued)
Byte
Number Function Described
30
Minimum RAS Pulse Width tRAS
31
Module Bank Density (Per Bank)
32
SDRAM Input Setup Time
33
SDRAM Input Hold Time
34
SDRAM Data Input Setup Time
35
SDRAM Data Input Hold Time
36-61 Superset Information (May be used in Future)
62
SPD Revision
63
Checksum for Bytes 0 - 62
64
Manufacturers JEDEC ID Code
65-71 Manufacturers JEDEC ID Code (cont.)
72
Manufacturing Location
73-90 Module Part Number (ASCII)
91-92 PCB Identification Code
93
Assembly Manufacturing Date (Year)
94
Assembly Manufacturing Date (Week)
95-98 Assembly Serial Number
99-125
126
127
128+
Reserved
Intel Specification for Frequency
Supported frequency
Unused Storage Location
Absolute Maximum Ratings
Parameter
Voltage on VDD Supply Relative to VSS
Voltage on Input Relative to VSS
Operating Temperature
Storage Temperature
Power Dissipation
V43658Y04VATG-75
SPD Entry Value
45 ns
64 MByte
1.5 ns
0.8 ns
1.5 ns
0.8 ns
Revision 1.2
Mosel Vitelic
1 = US, 2 = Taiwan
V43658Y04VATG-75
Current PCB Revision
Binary Coded year (BCD)
Binary Coded week (BCD)
byte 95 = LSB, byte 98 =
MSB
Hex Value
133 MHz
-75
2D
10
15
08
15
08
00
12
14
40
00
00
64
8D
00
Max.
-1 to 4.6
-1 to 4.6
0 to +70
-55 to 125
1.5
Units
V
V
°C
°C
W
V43658Y04VATG-75 Rev. 1.4 September 2001
5

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