NJU3505L 查看數據表（PDF） - Japan Radio Corporation

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NJU3505L

4-BIT SINGLE CHIP MICRO CONTROLLER

Japan Radio Corporation  

NJU3505

s INTERRUPT

The NJU3505 prepares four kinds of the interrupt. The interrupt "enable" or "disable" is controlled by the

program. The interrupt operates as single process and no multiple. However, when new interrupt request

occurs during the other interrupt process, the request is kept, and then the new interrupt process starts after

the prior interrupt process. The priority order of the interrupt is that the first is (1)External interrupt-1, the

second is (2)Internal interrupt-1, the third is (3)Internal interrupt-2, and the fourth is (4)Internal interrupt-3 as

shown below.

When the interrupt request flag is set by the own factor, the interrupt enabled by the interrupt control register

(PHY9) stores the data of Program Counter, Accumulator, X-reg, X'-reg, Y-reg, Y'-reg, RPC, and STATUS into

the STACK register, and sets the interrupt vector address into Program Counter, and then the interrupt process

is started. The return from the interrupt process by "RETI" instruction resets the corresponded interrupt

request flag, and regain the held data from STACK, and then the operation before the interrupt process is

started continuously. When the interrupt control register disables the interrupt process, the interrupt request

flag is not set.

[ THE PRIORITY ORDER OF FOUR INTERRUPTS ]

Order Interrupt

Vector Address(H:HEX)

(1) External interrupt-1

10H

(2) Internal interrupt-1 Timer/Counter-1 Overflow

20H

(3) Internal interrupt-2 Timer/Counter-2 Overflow

30H

(4) Internal interrupt-3 Serial shift register Full/Empty

40H

The External interrupt-1 enabled by PHY9 is started the interrupt process when the rising edge of signal pulse

is input to the external interrupt signal input terminal(EXTI). The External interrupt-1 request flag is reset by

'RETI' instruction. When the external interrupt-1 occurs during the standby mode by the HALT instruction, the

External interrupt-1 request signal is latched and its interrupt process is started after that the standby mode is

released.

The Internal interrupt enabled by PHY9 is started the interrupt process when the internal interrupt request flag

is set.

The Timer1 and the Timer2 interrupt request flags are independent of the overflow flag, and they are reset by

"RETI" instruction, (TIMER)START signal of the Timer control register, or RESET signal from the external

circuit. Serial Input Output interrupt request flag is set synchronizing with the transmission end flag when its

interrupt is enabled by PHY9. And the flag is reset by the "RETI" instruction or the RESET signal from the

external circuit.

• INTERRUPT CONTROL REGISTER { PHY9 ; (Y'=9) }

[ Writing to the Interrupt Control Register ]

(MSB) 3

2

1

0 (LSB)

PHY9

Serial shift register Full/Empty interrupt

(internal interrupt-3) control bit

/ 0:Disable 1:Enable

Timer2 Overflow interrupt

(internal interrupt-2) control bit

/ 0:Disable 1:Enable

Timer1 Overflow interrupt

(internal interrupt-1) control bit

/ 0:Disable 1:Enable

External interrupt-1 control bit

/ 0:Disable 1:Enable

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