NJW1146 查看數據表（PDF） - Japan Radio Corporation
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NJW1146 Datasheet PDF : 27 Pages
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NJW1146
s DEFINITION OF I2C REGISTER
q I2C BUS FORMAT
MSB
LSB MSB
LSB MSB
S Slave Address A Select Address A
1bit
8bit
1bit
8bit
1bit
S: Starting Term
A: Acknowledge Bit
P: Ending Term
q SLAVE ADDRESS
MSB
1
0
0
0
0
0
1
Data
8bit
LSB
AP
1bit 1bit
LSB
0
q CONTROL REGISTER TABLE
The select address sets each function (Volume, Balance, Bass Boost Select, AGC, Surround, Tone Control).
The auto-increment function cycles the select address as follows.
00H→01H→02H→03H→04H→05H→06H→00H
Select
Address
00H
01H
02H
03H
04H
05H
06H
D7
D6
CHS
BCB
BCT
eala
D5
BBEL
BBEH
BIT
D4
D3
D2
VOL
BAL
BASS
TREB
BBE
AGC
Don’t Care
D1
D0
Don’t Care
Don’t Care
Don’t Care
Don’t Care
AGC LVL
q CONTROL REGISTER DEFAULT VALUE
Control register default value is all “0”.
Select
BIT
Address
D7
D6
D5
D4
D3
D2
D1
D0
00H
0
0
0
0
0
0
0
0
01H
0
0
0
0
0
0
0
0
02H
0
0
0
0
0
0
0
0
03H
0
0
0
0
0
0
0
0
04H
0
0
0
0
0
0
0
0
05H
0
0
0
0
0
0
0
0
06H
0
0
0
0
0
0
0
0
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