NJW1148 查看數據表（PDF） - Japan Radio Corporation
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NJW1148 Datasheet PDF : 29 Pages
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PRELIMINARY
NJW1148
I I2C BUS CHARACTERISTICS (SDA, SCL)
I2C BUS Load Conditions: Pull up resistance 4kΩ (Connected to +5V), Load capacitance 200pF (Connected to GND)
PARAMETER
SYMBOL MIN. TYP. MAX. UNIT
Low Level Input Voltage
High Level Input Voltage
Hysteresis of Schmitt trigger inputs
LOW level output voltage (3mA at SDA pin)
Output fall time from VIHmin to VILmax with
a bus capacitance from 10pF to 400pF
Pulse width of spikes which must be suppressed by the input filter
Input current each I/O pin with an input voltage between 0.1VDD
and 0.9VDDmax
Capacitance for each I/O pin
SCL clock frequency
Hold time (repeated) START condition.
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
Noise margin at the LOW level
Noise margin at the HIGH level
VIL
VIH
Vhys
VOL
tof
tSP
Ii
Ci
fSCL
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
tf
tSU:STO
tBUF
Cb
VnL
VnH
0.0
-
1.5
V
3.0
-
5.0
V
0.25
-
-
V
0
-
0.4
V
20+0.1Cb
-
250
ns
0
-
50
ns
-10
-
10
µA
-
-
10
pF
-
-
400
kHz
0.6
-
-
µs
1.3
-
-
µs
0.6
-
-
µs
0.6
-
-
µs
-
-
0.9
µs
100
-
-
ns
-
-
300
ns
-
-
300
ns
0.6
-
-
µs
1.3
-
-
µs
-
-
400
pF
0.5
-
-
V
1
-
-
V
Cb ; total capacitance of one bus line in pF.
SDA
tf
tr
SCL
tHD:STA
S
tLOW
tf
tSU:DAT
tHD:STA
tHD:DAT
tHIGH
tSU:STA
Sr
tSP
tr
tBUF
tSU:STO
P
S
–5–
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