NJW1133A 查看數據表（PDF） - Japan Radio Corporation
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NJW1133A Datasheet PDF : 20 Pages
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NJW1133A
sDEFINITION OF I2C BUS REGISTER
qI2C BUS FORMAT
MSB
LSB MSB
LSB MSB
S Slave Address A Select Address A
1bit
8bit
1bit
8bit
1bit
S: Starting Term
A: Acknowledge
P: Ending Term
Data
8bit
LSB
AP
1bit 1bit
qSLAVE ADDRESS
MSB
LSB
1
0
0
0
0
0
1
R/W
R/W=0: Slave Receive
R/W=1: Not Output Data
qCONTROL REGISTER TABLE
The select address sets each function (Volume, Balance, AGC, Surround, Tone Control, AUX)
The auto increment function cycles the select address as follows.
00H¡01H¡02H¡03H¡04H¡05H¡00H
Select
Address
D7
D6
00H
01H
CHS
02H
BCB
03H
BCT
04H
05H
OUT
BIT
D5
D4
D3
VOL
BAL
BASS
TREB
Don’t Care
Don’t care
D2
D1
D0
BCSB
BCST
AGC
SUR
SUB-BASS
SUB-TREB
AUX1 AUX0
qCONTROL REGISTER DEFAULT VALUE
Control register default value is all “0”.
Select
Address
D7
D6
D5
00H
0
0
0
01H
0
0
0
02H
0
0
0
03H
0
0
0
04H
05H
0
0
0
BIT
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Don’t Care
0
0
0
0
0
Send the I2C BUS data after 30 ms from turn on.
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