NM24C08M 查看數據表（PDF） - Fairchild Semiconductor
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NM24C08M Datasheet PDF : 14 Pages
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AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
VCC x 0.1 to VCC x 0.9
10 ns
Input & Output Timing Levels VCC x 0.3 to VCC x 0.7
Output Load
1 TTL Gate and CL = 100 pF
AC Testing Input/Output Waveforms
0.9VCC
0.1VCC
0.7VCC
0.3VCC
DS500071-4
Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)
Symbol
Parameter
100 KHz
Min
Max
400 KHz
Min
Max
fSCL
SCL Clock Frequency
100
400
TI
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum VIN
100
50
Pulse width)
tAA
SCL Low to SDA Data Out Valid
0.3
3.5
0.1
0.9
tBUF
Time the Bus Must Be Free before
4.7
1.3
a New Transmission Can Start
tHD:STA
Start Condition Hold Time
4.0
0.6
tLOW
Clock Low Period
4.7
1.5
tHIGH
Clock High Period
4.0
0.6
tSU:STA
Start Condition Setup Time
4.7
0.6
(for a Repeated Start Condition)
tHD:DAT
Data in Hold Time
20
20
tSU:DAT
Data in Setup Time
250
100
tR
SDA and SCL Rise Time
1
0.3
tF
SDA and SCL Fall Time
300
300
tSU:STO
Stop Condition Setup Time
4.7
0.6
tDH
Data Out Hold Time
300
50
tWR
Write Cycle Time - NM24C08/09
10
10
(Note 3)
- NM24C08/09L, NM24C08/09LZ
15
15
Units
KHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
ms
Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM24C08/09 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer
"Write Cycle Timing" diagram.
Bus Timing
tF
tR
tHIGH
tLOW
tLOW
SCL
SDA
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
;;IN
tAA
SDA
OUT
tDH
tBUF
DS500071-5
NM24C08/09 Rev. G
5
www.fairchildsemi.com
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