P4C163-25CMLF 查看數據表（PDF） - Semiconductor Corporation

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P4C163-25CMLF

ULTRA HIGH SPEED 8K x 9 STATIC CMOS RAMS

Semiconductor Corporation 

READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)

READ CYCLE NO. 3 (CE1, CE2 CONTROLLED)(5,7,10)

P4C163/163L

Notes:

9. READ Cycle Time is measured from the last valid address to the first

transitioning address.

10. Transitions caused by a chip enable control have similar delays

irrespective of whether CE1 or CE2 causes them.

Document # SRAM120 REV C

Page 5 of 12

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