P4C164L-100CMB 查看數據表（PDF） - Semiconductor Corporation

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P4C164L-100CMB

ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS

Semiconductor Corporation 

P4C164

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(11)

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(11)

Notes:

11.

CE

1

and

WE

must

be

LOW,

and

CE2

HIGH

for

WRITE

cycle.

12. OE is LOW for this WRITE cycle to show tWZ and tOW.

13.

If

CE

1

goes

HIGH,

or

CE2

goes

LOW,

simultaneously

with

WE

HIGH,

the output remains in a high impedance state.

14. Write Cycle Time is measured from the last valid address to the first

transitioning address.

Document # SRAM115 REV F

Page 6 of 16

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