PCA9558 查看數據表（PDF） - NXP Semiconductors.
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PCA9558 Datasheet PDF : 27 Pages
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NXP Semiconductors
PCA9558
8-bit I2C-bus/SMBus I/O port
Table 2. Pin description …continued
Symbol
Pin
Description
MUX_SELECT
19
active LOW select of MUX_INx inputs or EEPROM contents
for MUX_OUTx outputs
MUX_OUTE
20
open-drain multiplexed output E
MUX_OUTD
21
open-drain multiplexed output D
MUX_OUTC
22
open-drain multiplexed output C
MUX_OUTB
23
open-drain multiplexed output B
MUX_OUTA
24
open-drain multiplexed output A
NON_MUXED_OUT 25
open-drain outputs from non-volatile memory
MUX_OUT_LOW
26
active LOW control forces all MUX outputs to logic 0
WP
27
active HIGH EEPROM write protect
VDD
28
power supply (3.0 V to 3.6 V)
7. Functional description
Refer to Figure 1 “Block diagram of PCA9558”.
7.1 I2C-bus interface
Communicating with this device is initiated by sending a valid address on the I2C-bus. The
address format (see Figure 3) has 6 fixed bits and one user-programmable bit followed by
a 1-bit read/write value which determines the direction of the data transfer.
MSB
LSB
1 0 0 1 1 1 A0 R/W
fixed
Fig 3. I2C-bus address byte
hardware
selectable
002aad367
Following the address and acknowledge bit are 8 data bits which, depending on the
read/write bit in the address, will read data from or write data to the EEPROM. Data will be
written to the register if the read/write bit is logic 0 and the WP input is logic 0. Data will be
read from the register if the bit is logic 1. The four high-order bits are latched outputs,
while the four low order bits are multiplexed outputs (Figure 5).
Remark: To ensure data integrity, the EEPROM must be internally write protected when
VDD to the I2C-bus is powered down or VDD to the component is dropped below normal
operating levels.
Fig 4. Command byte
D7 D6 D5 D4 D3 D2 D1 D0
002aad368
PCA9558_4
Product data sheet
Rev. 04 — 14 April 2009
© NXP B.V. 2009. All rights reserved.
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