PCA9558 查看數據表（PDF） - NXP Semiconductors.

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PCA9558

8-bit I2C-bus and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C-bus EEPROM DIP switch and 2-kbit EEPROM

NXP Semiconductors. 

NXP Semiconductors

PCA9558

8-bit I2C-bus/SMBus I/O port

slave address

command byte

data byte

S 1 0 0 1 1 1 A0 0 A 0 0 0 0 1 0 1 1 A 0 0 0 0 0 0 B1 B0 A P

START condition

R/W acknowledge

from slave

Fig 7. I2C-bus write for MUXCNTRL register

acknowledge

from slave

acknowledge STOP

from slave condition

002aad371

slave address

command byte

slave address

S 1 0 0 1 1 1 A0 0 A 0 0 0 0 1 0 1 1 A S 1 0 0 1 1 1 A0 1 A (cont.)

START condition

R/W acknowledge

from slave

acknowledge (re)START

from slave condition

R/W acknowledge

from slave

data from slave

(cont.) 0 0 0 0 0 0 B1 B0 NA P

Fig 8. I2C-bus read for MUXCNTRL register

no acknowledge STOP

from master condition

002aad372

7.1.2 Registers

The GPIOs are controlled by a set of 4 internal registers: Input Port (IP) register; Output

Port (OP) register; Polarity Inversion (PI) register; and the Input/Output Configuration

(IOC) register. Each register is read/write via the I2C-bus or 256-byte EEPROM, with the

exception of the Input Port register, which is read only, one at a time. The read/write takes

place on the slave Acknowledge. The control of which register is currently available to the

I2C-bus is set by bits in the control register. See Section 7.1.2.1 through Section 7.1.2.4

for details.

7.1.2.1 IP - Input Port register

This register is an input-only port. It reflects the logic value present on the GPIO pins

regardless of whether they are configured as inputs or outputs (IOC register). Writes to

this register have no effect.

Table 5. IP - Input Port register description

Bit

7

6

5

4

3

2

1

0

Symbol

I7

I6

I5

I4

I3

I2

I1

I0

Default

0

0

0

0

0

0

0

0

PCA9558_4

Product data sheet

Rev. 04 — 14 April 2009

© NXP B.V. 2009. All rights reserved.

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