Philips Semiconductors
I2C-bus controller
Product specification
PCF8584
12 I2C-BUS TIMING SPECIFICATIONS
All the timing limits are valid within the operating supply voltage and ambient temperature range; VDD = 5 V ±10%;
Tamb = −40 to +85 °C; and refer to VIL and VIH with an input voltage of VSS to VDD.
SYMBOL
PARAMETER
MIN.
TYP.
MAX. UNIT
fSCL
tSW
tBUF
tSU;STA
tHD;STA
tLOW
tHIGH
tr
tf
tSU;DAT
tHD;DAT
tVD;DAT
tSU;STO
SCL clock frequency
tolerable spike width on bus
bus free time
START condition set-up time
START condition hold time
SCL LOW time
SCL HIGH time
SCL and SDA rise time
SCL and SDA fall time
data set-up time
data hold time
SCL LOW to data out valid
STOP condition set-up time
−
−
−
−
4.7
−
4.7
−
4.0
−
4.7
−
4.0
−
−
−
−
−
250
−
0
−
−
−
4.0
−
100
kHz
100
ns
−
µs
−
µs
−
µs
−
µs
−
µs
1.0
µs
0.3
µs
−
ns
−
ns
3.4
µs
−
µs
13 PARALLEL INTERFACE TIMING
All the timing limits are valid within the operating supply voltage and ambient temperature range: VDD = 5 V ±10%;
Tamb = −40 to +85 °C; and refer to VIL and VIH with an input voltage of VSS to VDD. CL = 100 pF; RL = 1.5 kΩ
(connected to VDD) for open-drain and high-impedance outputs, where applicable (for measurement purposes only).
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
tr
clock rise time
see Fig.14
−
−
tf
clock fall time
see Fig.14
−
−
tCLK
input clock period
(50% ±5% duty factor)
see Fig.14
83
−
tCLRL
CS set-up to RD LOW
see Fig.16 and note 1 20
−
tCLWL
CS set-up to WR LOW
see Fig.15 and note 1 20
−
tRHCH
CS hold from RD HIGH
see Fig.16
0
−
tWHCH
CS hold from WR HIGH
see Fig.15
0
−
tAVWL
A0 set-up to WR LOW
see Fig.15
10
−
tAVRL
A0 set-up to RD LOW
see Fig.16
10
−
tWHAI
A0 hold from WR HIGH
see Fig.15
20
−
tRHAI
A0 hold from RD HIGH
see Fig.16
10
−
tWLWH
WR pulse width
see Fig.15
230
−
tRLRH
RD pulse width
see Fig.16
230
−
tDVWH
data set-up before WR HIGH see Fig.15
150
−
tRLDV
data valid after RD LOW
see Fig.16
−
160
tWHDI
data hold after WR HIGH
see Fig.15
20
−
tRHDF
data bus floating after RD
HIGH
see Fig.16
−
−
6
ns
6
ns
333
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
1 000
ns
1 000
ns
−
ns
180
ns
−
ns
150
ns
1997 Oct 21
24