PD45128163-SU 查看數據表（PDF） - Elpida Memory, Inc

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PD45128163-SU

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Elpida Memory, Inc 

µPD45128163-SU

12.2 Precharge Termination

12.2.1 Precharge Termination in READ Cycle

During a read cycle, the burst read operation is terminated by a precharge command.

When the precharge command is issued, the burst read operation is terminated and precharge starts.

The same bank can be activated again after tRP from the precharge command.

To issue a precharge command, tRAS must be satisfied.

When /CAS latency is 2, the read data will remain valid until one clock after the precharge command.

Burst length = X, /CAS latency = 2

T0

T1

T2

T3

T4

T5

T6

T7

CLK

Command

READ

PRE

ACT

Hi-Z

DQ

Q1

Q2

Q3

Q4

tRP

(tRAS must be satisfied)

When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command.

Burst length = X, /CAS latency = 3

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

Command

READ

PRE

ACT

Hi-Z

DQ

Q1

Q2

Q3

Q4

tRP

(tRAS must be satisfied)

30

Preliminary Data Sheet E0242N10

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