PDI1394L21 查看數據表（PDF） - Philips Electronics
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PDI1394L21 Datasheet PDF : 52 Pages
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ERRATA LIST FOR THE PHILIPS
PDI1394L21 1394 FULL DUPLEX AV LINK LAYER CONTROLLER
(These errata refer to the data sheet dated 1999 August 6)
Chip Errata:
E-1. Self-ID Packet Issues:
Description of expected operation: After bus reset, the queues are flushed and a self-ID packet should be
placed in the Read Request Queue. Refer to section 12.5.2.4 (Self-ID and PHY packets receive) in the
“PDI1394L21 1394 Full Duplex AV Link Layer Controller” data sheet for the proper format of a self-ID packet.
Description of observed behavior: Occasionally 0x000000E0 and 0x00000010 quadlets are found in the Read
Request Queue with no accompanying self-ID and acknowledge quadlet. This type of self-ID is valid ONLY for a
node which is not connected to any other node (node standing alone). This partial self-ID packet results from a
recent node connection (hot plug) event or Link/PHY hardware reset.
Solution or work around: Issue a software bus reset and read the self IDs generated by that reset.
E-2. AVFSYNC pin function at high FSYNC pulse repetition rates:
Description of expected operation: With the EN_FS bits set on the isochronous transmitter of the transmitting
node and the isochronous receiver of the receiving node, a pulse introduced at the FSYNC pin on the transmitting
AV port of the transmitting node will produce an SYT field time stamp in the next bus packet which will, in turn,
produce a pulse at the FSYNC pin of the receiving AV port on the receiving node at a time corresponding to the
expiration of the SYT field time stamp, with the SYT Delay introduced at the transmitter taken into account.
Description of observed behavior: At rep rates below 2 KHz, the system works as expected. At rep rates
greater than 2 KHz (dependant upon the setting of the SYT Delay bits) the system operates as expected for a
short period of time (about 100 milliseconds), then operates erratically thereafter.
Solution or work around: Do not use above the following rep rates with the corresponding SYT Delay settings:
SYT Delay = 2 bus cycles, maximum rep rate = 3,200; SYT Delay = 3 bus cycles, maximum rep rate = 3,200;
SYT Delay = 4 bus cycles, maximum rep rate = 4,200.
E-3. AVENKEY pin function:
Description of expected operation: This pin / function is intended to attach a specific “key” state to each byte of
a transmitted isochronous packet by means of reading the ENKEY pin on the transmitting AV port while the first
byte of an application packet is being inputted. The ENKEY state of the first inputted byte is the state of all packet
bytes.
Description of observed behavior: Unless the state of the ENKEY pin is inputted within a certain part of the link
internal clock cycle, occasionally some of the bytes in a packet are keyed with the wrong state. This results in
packets getting “stuck” in the isochronous transmit FIFO and causing FIFO overfill.
Solution or work around: Input key states only with reference to the CLK25 signal of the link chip to assure
proper synchronization. The AVCLK signal must rise 8 to 41 nS before the CLK25 signal rises for proper
operation at 12.288 MHz. It is the AVCLK signal which introduces the state of the ENKEY pin (and all
others) to the AV port interface logic. Please consult Philips IEEE 1394 Applications Engineering Group
(1394@philips.com) for use of this function at other AVCLK frequencies.
Philips Semiconductors
Errata To the PDI1394L21 1394 Full Duplex AV Link Layer Controller (Data Sheet dated: 1999 August 6).
August 6, 1999
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