PDI1394P23 查看數據表（PDF） - Philips Electronics
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PDI1394P23 Datasheet PDF : 42 Pages
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Philips Semiconductors
2-port/1-port 400 Mbps physical layer interface
Preliminary data
PDI1394P23
17.1 External Component Connections
REFER TO SECTION 17.5
12 pF
12 pF
24.576 MHz
VDD
0.1 µF
0.001 µF
CONNECT RESET TO THE SAME SOURCE AS THE LINK IC
OR THROUGH OPTOCOUPLER FOR GALVANIC ISOLATION.
USE 0.1 µF CAPACITOR TO GND ONLY IN NON-LINK DESIGNS.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
CNA OUT
POWER DOWN
LINK PULSE OR
LINK VDD OR VDD
(REFER TO
FIGURES 7 AND 8)
1 LREQ
2 SYSCLK
3 CNA
4 CTL0
5 CTL1
6 D0
7 D1
8 D2
9 D3
10 D4
11 D5
12 D6
13 D7
14 PD
15 LPS
16 NC
PDI1394P23
AGND 48
TPBIAS1 47
TPA1+ 46
TPA1– 45
TPB1+ 44
TPB1– 43
AVDD 42
R1 41
R0 40
AGND 39
TPBIAS0 38
TPA0+ 37
TPA0– 36
TPB0+ 35
TPB0– 34
AGND 33
0.3–1.0 µF
TPBIAS
TP CABLES
INTERFACE CONNECTION
(REFER TO FIGURES 4 AND 5)
6.34 kΩ ±1%
0.3–1.0 µF
TPBIAS
TP CABLES
INTERFACE CONNECTION
(REFER TO FIGURES 4 AND 5)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
390 kΩ
See Figure 6 for recommended power and ground connections.
Figure 10. External Component Connections
2001 Sep 06
22
SV001872
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