9704-11 查看數據表（PDF） - Peregrine Semiconductor Corp.
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9704-11 Datasheet PDF : 11 Pages
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Figure 2. Pin Configuration
R4
R5
M0
M1
VDD
VDD
M2
M3
S_W R, M4
DATA, M5
GND
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
CEXT
VDD
PD_U
PD_D
GND
N/C
VDD
DOUT
VDD
N/C
GND
PE9704
Advance Information
Table 1. Pin Descriptions
Pin No. Pin Name Interface Mode
Type
1
VDD
Both
2
R0
3
R1
4
R2
5
R3
6
GND
7
R4
8
R5
9
M0
10
M1
11
VDD
12
VDD
13
M2
14
M3
Direct
Direct
Direct
Direct
Both
Direct
Direct
Direct
Direct
Both
Both
Direct
Direct
S_WR
Serial
15
M4
Direct
(Note 1)
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
(Note 1)
(Note 1)
Input
Input
Input
Input
16
DATA
Serial
Input
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
R Counter bit0
R Counter bit1
R Counter bit2
R Counter bit3
Ground
R Counter bit4
R Counter bit5 (MSB)
M Counter bit0
M Counter bit1
Same as pin 1
Same as pin 1
M Counter bit2
M Counter bit3
Frequency register load enable input. Buffered data is transferred to the frequency
register on S_WR rising edge.
M Counter bit4
Binary serial data input. Data is entered LSB first, and is clocked serially into the 20-
bit frequency control register (E_WR “low”) or the 8-bit enhancement register (E_WR
“high”) on the rising edge of CLOCK.
Copyright Peregrine Semiconductor Corp. 2003
Page 2 of 12
File No. 70/0083~00B | | UTSi CMOS RFIC SOLUTIONS
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