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LC865520B 查看數據表(PDF) - SANYO -> Panasonic

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产品描述 (功能)
比赛名单
LC865520B Datasheet PDF : 21 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
LC865520B/16B/12B/08B/04B
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=0V
Parameter
Operating
Supply
voltage range
Hold voltage
Symbol
VDD(1)
VDD(2)
VHD
Input high
voltage
VIH(1)
VIH(2)
VIH(3)
VIH(4)
VIH(5)
Input low
voltage
VIH(6)
VIH(7)
VIL(1)
VIL(2)
VIL(3)
VIL(4)
VIL(5)
VIL(6)
Operation
cycle time
Oscillation
frequency
range
(Note 1)
tCYC
FmCF(1)
FmCF(2)
FmRC
FsXtal
Pins
VDD
Conditions
Ratings
unit
VDD[V] min. typ. max.
0.98µs tCYC 400µs
4.5
6.0 V
3.9µs tCYC 400µs
2.5
6.0
VDD
RAM and register data
2.0
6.0
are kept in HOLD
mode.
Port 0 of CMOS output Output disable
2.5 to 6.0 0.33VDD
VDD
+1.0
Port 0 of N-ch open Output disable
4.0 to 6.0 0.75VDD
13.5
drain output
2.5 to 4.0 0.8VDD
13.5
• Port 1
Output disable
2.5 to 6.0 0.75VDD
VDD
• Ports 72,73
• Port 3 of CMOS
output
Port 3 of N-ch open Output disable
4.0 to 6.0 0.75VDD
13.5
drain output
2.5 to 4.0 0.8VDD
13.5
• Port 70
Output disable
2.5 to 6.0 0.75VDD
VDD
Port input/interrupt
• Port 71
RES
Port 70
Output disable
2.5 to 6.0 0.9VDD
VDD
Watchdog timer
• Port 8
• Output disable
2.5 to 6.0 0.75VDD
VDD
• Ports 74,75
• Using as port
Port 0 of CMOS output Output disable
2.5 to 6.0 VSS
0.2VDD
Port 0 of N-ch open Output disable
2.5 to 6.0 VSS
0.25VDD
drain output
• Ports 1,3
Output disable
2.5 to 6.0 VSS
0.25VDD
• Ports 72,73
• Port 70
Output disable
2.5 to 6.0 VSS
0.25VDD
Port input/interrupt
• Port 71
RES
Port 70
Output disable
2.5 to 6.0 VSS
0.8VDD
Watchdog timer
to 1.0
• Port 8
• Output disable
2.5 to 6.0 VSS
0.25VDD
• Ports 74,75
• Using as port
4.5 to 6.0 0.98
400 µs
2.5 to 6.0 3.9
400
CF1, CF2
• 6MHz
4.5 to 6.0 5.88 6 6.12 MHz
(ceramic resonator)
• Refer to figure 1
CF1, CF2
•3MHz
2.5 to 6.0 2.94 3 3.06
(ceramic resonator)
• Refer to figure 1
Internal RC oscillation 2.5 to 6.0 0.3 0.8 3.0
XT1, XT2
•32.768kHz
2.5 to 6.0
32.768
kHz
(crystal oscillation)
• Refer to figure 2
Continue.
No.6697-11/21

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