LC865520B/16B/12B/08B/04B
VDD
RRES
(Note) Select CRES and RRES value to assure that
at least 200µs reset time is generated after
the VDD becomes higher than the minimum
RES
operating voltage.
CRES
Figure 4 Reset circuit
SCK0
SCK1
SI0
SI1
SO0, SO1
SB0, SB1
0.5VDD
<AC timing point>
tCKL
tCKCY
tCKH
tICK tCKI
VDD
1kΩ
tCKO
50pF
<Timing>
<Test load>
Figure 5 Serial input / output test condition
tPIL
tPIH
Figure 6 Pulse input timing condition
No.6697-20/21