PIC16F716 查看數據表（PDF） - Microchip Technology

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PIC16F716

8-bit Flash-based Microcontroller with A/D Converter and Enhanced Capture/Compare/PWM

Microchip Technology 

2.3 PCL and PCLATH

The Program Counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 13 bits

wide. The low byte is called the PCL register. This

register is readable and writable. The high byte is

called the PCH register. This register contains the

PC<12:8> bits and is not directly readable or writable.

All updates to the PCH register go through the PCLATH

register.

2.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<12:8> bits (PCH) to be replaced by the

contents of PCLATH register. This allows the entire

contents of the program counter to be changed by first

writing the desired upper 5 bits to the PCLATH register.

When the lower 8 bits are then written to the PCL

register, all 13 bits of the program counter will change

to the values contained in the PCLATH register and

those being written to the PCL register.

Care should be exercised when modifying the PCL

register to jump into a look-up table or program branch

table (computed GOTO). With PCLATH set to the table

start address, if the table is greater than 255

instructions or if the lower 8 bits of the memory address

rolls over from 0xFF to 0x00 in the middle of the table,

then PCLATH must be incremented for each address

rollover that occurs between the table beginning and

the target address.

2.3.2 PROGRAM MEMORY PAGING

The CALL and GOTO instructions provide 11 bits of

address to allow branching within any 2K program

memory page. When doing a CALL or GOTO instruction,

the upper bit of the address is provided by

PCLATH<3>. When doing a CALL or GOTO instruction,

the user must ensure that the page select bit is

programmed so that the desired program memory

page is addressed. If a RETURN from a CALL instruction

(or interrupt) is executed, the entire 13-bit PC is pushed

onto the stack. Therefore, manipulation of the

PCLATH<3> bit is not required for the RETURN

instructions (which POPs the address from the stack).

PIC16F716

FIGURE 2-3:

LOADING OF PC IN

DIFFERENT SITUATIONS

PCH

12

87

PCLATH<4:0>

5

PCL

0 Instruction with

PCL as

8

Destination

ALU

PCLATH

PCH

12 1110

87

PCLATH<4:3>

2

PCL

0

GOTO, CALL

11

Opcode <10:0>

PCLATH

2.4 Stack

The stack allows a combination of up to 8 program calls

and interrupts to occur. The stack contains the return

address from this branch in program execution.

Mid-range devices have an 8-level deep x 13-bit wide

hardware stack. The stack space is not part of either

program or data space, and the stack pointer is not

readable or writable. The PC is PUSHed onto the stack

when a CALL instruction is executed or an interrupt

causes a branch. The stack is POPed in the event of a

RETURN, RETLW or a RETFIE instruction execution.

PCLATH is not modified when the stack is PUSHed or

POPed.

After the stack has been PUSHed 8 times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

 2003 Microchip Technology Inc.

Preliminary

DS41206A-page 17

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