HI5675(1999) 查看數據表（PDF） - Intersil

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HI5675
(Rev.:1999)

8-Bit, 20MSPS, Flash A/D Converter

Intersil 

HI5675

Static Performance Definitions

Offset, full scale, and gain all use a measured value of the

internal voltage reference to determine the ideal plus and

minus full scale values. The results are all displayed in LSBs.

Offset Error (EOB)

The first code transition should occur at a level 1/2LSB

above the bottom reference voltage. Offset is defined as the

deviation of the actual code transition from this point. Note

that this is adjustable to zero.

Full Scale Error (EOT)

The last code transition should occur for a analog input that

is 11/2 LSBs below full scale. Full scale error is defined as

the deviation of the actual code transition from this point.

Differential Linearity Error (DNL)

DNL is the worst case deviation of a code width from the

ideal value of 1 LSB. The converter is guaranteed to have no

missing codes.

Integral Linearity Error (INL)

INL is the worst case deviation of a code center from a best

fit straight line calculated from the measured data.

Dynamic Performance Definitions

Fast Fourier Transform (FFT) techniques are used to

evaluate the dynamic performance of the HI5675. A low

distortion sine wave is applied to the input, it is sampled, and

the output is stored in RAM. The data is then transformed

into the frequency domain with a 1024 point FFT and

analyzed to evaluate the dynamic performance of the A/D.

The sine wave input to the part is -0.5dB down from fullscale

for all these tests. The distortion numbers are quoted in dBc

(decibels with respect to carrier) and DO NOT include any

correction factors for normalizing to fullscale.

Signal-to-Noise Ratio (SNR)

SNR is the measured RMS signal to RMS noise at a

specified input and sampling frequency. The noise is the

RMS sum of all of the spectral components except the

fundamental and the first five harmonics.

Signal-to-Noise + Distortion Ratio (SINAD)

SINAD is the measured RMS signal to RMS sum of all

other spectral components below the Nyquist frequency

excluding DC.

Effective Number Of Bits (ENOB)

The effective number of bits (ENOB) is derived from the

SINAD data. ENOB is calculated from:

ENOB = (SINAD - 1.76 + VCORR) / 6.02,

where: VCORR = 0.5dB.

Total Harmonic Distortion

This is the ratio of the RMS sum of the first 5 harmonic

components to the RMS value of the measured input signal.

2nd and 3rd Harmonic Distortion

This is the ratio of the RMS value of the 2nd and 3rd

harmonic component respectively to the RMS value of the

measured input signal.

Spurious Free Dynamic Range (SFDR)

SFDR is the ratio of the fundamental RMS amplitude to the

RMS amplitude of the next largest spur or spectral

component. If the harmonics are buried in the noise floor it is

the largest peak.

Full Power Input Bandwidth

Full power bandwidth is the frequency at which the

amplitude of the digitally reconstructed output has

decreased 3dB below the amplitude of the input sine wave.

The input sine wave has a peak-to-peak amplitude equal to

the reference voltage. The bandwidth given is measured at

the specified sampling frequency.

Timing Definitions

Sampling Delay (tSD)

Sampling delay is the time delay between the external

sample command (the falling edge of the clock) and the time

at which the signal is actually sampled. This delay is due to

internal clock path propagation delays.

Aperture Jitter (tAJ)

This is the RMS variation in the sampling delay due to

variation of internal clock path delays.

Data Latency (tLAT)

After the analog sample is taken, the data on the bus is

available after 2.5 cycles of the clock. This is due to the

architecture of the converter where the data has to ripple

through the stages. This delay is specified as the data

latency. After the data latency time, the data representing

each succeeding sample is output at the following clock

pulse. The digital data lags the analog input by 2.5 cycles.

Output Data Delay (tD)

Output Data Delay is the delay time from when the data is

valid (rising clock edge) to when it shows up at the output

bus. This is due to internal delays at the digital output.

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