PLL102-15 查看數據表（PDF） - PhaseLink Corporation
零件编号
产品描述 (功能)
比赛名单
PLL102-15 Datasheet PDF : 8 Pages
| |||
PLL102-15
Low Skew Output Buffer
REVISION HISTORY
06/20/01
10/23/01
11/07/01
11/29/01
10/08/02
01/13/03
05/06/03
Created from preliminary PLL102 -05 and PLL102-04 Document
Removed Power Down mode in absence of REF (not supported in final version).
Added VDD = 3.3V in Electrical Specs for clarity.
Added Remark on REF clock absence on page 1
Change pass through modulation rate from 100kHz to 33kHz.
Changed Frequency range from “25-75MHz” to “25-60MHz” on Features section on page 1
Changed Supply Current (IDD) from Unloaded outputs at “66.67MHz” to “60MHz” on page 3
Changed Max. of Output Frequency from “75” to “60” on page 4
Deleted “Fout < 50.0MHz” for Duty Cycle (Dt2) and “Measured at 60MHz” for Cycle to Cycle Jitter
(Tcyc -cyc) of Switching Characteristics section on page 4
Bonding diagram modification to P102 -15 (ICS553 compatible)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 05/06/03 Page 8
Share Link: 