PLL103-02(2004) 查看數據表（PDF） - PhaseLink Corporation
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PLL103-02 Datasheet PDF : 6 Pages
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PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
PIN DESCRIPTIONS
Name
FBOUT
BUF_IN
PD
N/C
DDR[0:11]T
DDR[0:11]C
VDD2.5
GND
Number
1
13
36
48
4,6,10,15,19,
21,28,30,34,
39,43,45
5,7,11,16,20,
22,27,29,33,
38,42,44
2,8,12,17,23,
32,37,41,47
3,9,14,18,26,
31,35,40,46
Type
Description
O Feedback clock for chipset.
I Reference input from chipset.
I Power Down Control input. When low, it will tri-state all outputs.
Not connected.
O These outputs provide True copies of BUF_IN.
O These outputs provide complementary copies of BUF_IN.
P 2.5V power supply.
P Ground.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 2
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