GLT6100L08LL-100TC 查看數據表（PDF） - G-Link Technology
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GLT6100L08LL-100TC Datasheet PDF : 10 Pages
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G-LINK
GLT6100L16
Ultra Low Power 64k x 16 CMOS SRAM
May 2000(Rev. 0.3)
Notes :
1. L-version includes this feature.
2. This Parameter is samples and not 100% tested.
3. For test conditions, see AC Test Condition.
4. This parameter is tested with CL = 5pF. Transition is measured ± 500mV from steady – state voltage.
5. This parameter is guaranteed, but is not tested.
6. WE is HIGH for read cycle.
7. CE and OE are LOW for read cycle.
8. Address valid prior to or coincident with CE transition LOW.
9. All read cycle timings are referenced from the last valid address to the first transition address.
10. CE or WE must be HIGH during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
12. WE are high for read cycle.
13. All read cycle timing is referenced from the last valid address to the first transition address.
14. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL
levels.
15. At any given temperature and voltage condition tHZ(max.) is less than tLZ (min.) both for a given device and from
device to device.
16. Transition is measured ± 200mV from steady state voltage with load. This parameter is sampled and not 100%
tested.
17. Device is continuously selected with CE = VIL.
18. Address valid prior to coincident with CE transition Low.
19. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read
write cycle.
20. For test conditions, see AC Test Condition.
21. All write timing is referenced from the last valid address to the first transition address.
22. A write occurs during the overlap of a low CE and WE . A write begins at the latest transition among CE and
WE going low: A write ends at the earliest transition among CE going high and WE going high. tWP is
measured from the beginning of write to the end of write.
23. tCW is measured from the later of CE going low to end of write.
24. tAS is measured from the address valid to the beginning of write.
25. tWR is measured from the end of write to the address change.
26. If OE , CE and WE are in the Read Mode during this period, the I/O pins are in the output Low-Z state.
27. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read
and write cycle.
28. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain high
impedance state.
29. DOUT is the read data of the new address.
30. When CE is low : I/O pins are in the outputs state. The input signals in the opposite phase leading to the output
should not be applied.
31. For test conditions, see AC Test Condition.
G-Link Technology Corporation
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Santa Clara, CA 95051, U.S.A.
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