RT8065 查看數據表（PDF） - Richtek Technology
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RT8065 Datasheet PDF : 13 Pages
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RT8065
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
SOP-8 (Exposed Pad) packages, the thermal resistance,
θJA, is 75°C/W on a standard JEDEC 51-7 four-layer
thermal test board. For WDFN-8L 3x3 packages, the
thermal resistance, θJA, is 70°C/W on a standard JEDEC
51-7 four-layer thermal test board. The maximum power
dissipation at TA =25°C can be calculated by the following
formulas :
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of the IC.
` Connect the terminal of the input capacitor(s), CIN, as
close to the VIN pin as possible. This capacitor provides
the AC current into the internal power MOSFETs.
` LX node experiences high frequency voltage swings so
should be kept within a small area.
` Keep all sensitive small signal nodes away from the LX
node to prevent stray capacitive noise pick up.
` Connect the FB pin directly to the feedback resistors.
The resistive voltage-divider must be connected between
VOUT and GND.
Place the compensation
components as close to
the IC as possible
Place the feedback
resistors as close to
the IC as possible
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for
GND
SOP-8 (Exposed Pad) package
PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for
WDFN-8L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. The derating curves in Figure 3 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
CCOMP
CSS
COMP
RCOMP
SS
EN
VIN
GND
VIN
CIN
8
2
7
GND
3
96
4
5
PGOOD
FB
RT
LX
COUT
L1
VOUT
Place the input and output capacitors
as close to the IC as possible
R2
R1 VOUT
ROSC GND
LX should be connected
to inductor by wide and
short trace, and keep
sensitive components
away from this trace
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
Four-Layer PCB
Place the compensation
components as close to
the IC as possible
Place the feedback
resistors as close to
the IC as possible
WDFN-8L 3x3
SOP-8 (Exposed Pad)
25
50
75
100
GND
CCOMP
RCOMP
COMP 1
SS 2
R2
8 PGOOD R1
7 FB
VOUT
CSS
GND
EN 3
VIN 4
CIN
VIN
6 RT
9 5 LX
ROSC GND
LX should be connected
COUT
L1
to inductor by wide and
short trace, and keep
sensitive components
VOUT
away from this trace
Place the input and output capacitors
125
as close to the IC as possible
Ambient Temperature (°C)
Figure 3. Derating Curve of Maximum Power Dissipation
Figure 4. PCB Layout Guide
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
DS8065-07 November 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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