RT9514 查看數據表（PDF） - Richtek Technology

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RT9514

Linear Single Cell Li-Ion Battery Charger IC

Richtek Technology 

RT9514

Temperature Regulation

In order to maximize the charge rate, the RT9514 features

a junction temperature regulation loop. If the power

dissipation of the IC results in a junction temperature

greater than the thermal regulation threshold (125°C), the

RT9514 throttles back on the charge current in order to

maintain a junction temperature around the thermal

regulation threshold (125°C). The RT9514 monitors the

junction temperature, TJ, of the die and disconnects the

battery from the input if TJ exceeds 125°C. This operation

continues until junction temperature falls below thermal

regulation threshold (125°C) by the hysteresis level. This

feature prevents the chip from damaging.

Selecting the Input and Output Capacitors

In most applications, the most important is the high-

frequency decoupling capacitor on the input of the RT9514.

A 1uF ceramic capacitor, placed in close proximity to input

pin and GND pin is recommended. In some applications

depending on the power supply characteristics and cable

length, it may be necessary to add an additional 10uF

ceramic capacitor to the input. The RT9514 requires a

small output capacitor for loop stability. A 1uF ceramic

capacitor placed between the BATT pin and GND is typically

sufficient.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum operation junction temperature. The maximum

power dissipation depends on the thermal resistance of

IC package, PCB layout, the rate of surroundings airflow

and temperature difference between junction to ambient.

The maximum power dissipation can be calculated by

following formula :

PD(MAX) = ( TJ(MAX) - TA ) / θJA

Where TJ(MAX) is the maximum operation junction

temperature 125°C, TA is the ambient temperature and the

θJA is the junction to ambient thermal resistance.

For recommended operating conditions specification,

where TJ(MAX) is the maximum junction temperature of the

die (125°C) and TA is the ambient temperature. The junction

to ambient thermal resistance θJA is layout dependent.

For WDFN-10L 3x3 packages, the thermal resistance θJA

is 60°C/W on the standard JEDEC 51-7 four layers thermal

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test board. The maximum power dissipation at TA = 25°C

can be calculated by following formula :

PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.667W for

WDFN-10L 3x3 packages

The maximum power dissipation depends on operating

ambient temperature for fixed TJ(MAX) and thermal

resistance θJA. For WDFN-10L 3x3 package, the Figure 2

of derating curves allows the designer to see the effect of

rising ambient temperature on the maximum power

allowed.

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

0

Four Layers PCB

WDFN-10L 3x3

25

50

75

100

125

Ambient Temperature (°C)

Figure 2. Derating Curves for RT9514 Package

Layout Considerations

For the best performance of the RT9514, the following

PCB layout guidelines must be strictly followed.

` Place the input and output capacitors as close as

possible to the input and output pins respectively for

good filtering.

` Keep the main power traces as wide and short as

possible.

` The connection of RSETA should be isolated from other

noisy traces. The short wire is recommended to prevent

EMI and noise coupling.

` Connect the GND and Exposed Pad to a strong ground

plane for maximum thermal dissipation and noise

protection.

DS9514-01 April 2011

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