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RTL8181 查看數據表(PDF) - Realtek Semiconductor

零件编号
产品描述 (功能)
比赛名单
RTL8181
Realtek
Realtek Semiconductor Realtek
RTL8181 Datasheet PDF : 50 Pages
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The read access timing of flash memory:
A[20..0]
F_CE0#
WE#
OE#
D[n..0]
RTL8181
8. Ethernet Controller
There are two 10/100M Ethernet MAC embedded in RTL8181. The Ethernet device has bus master capability, which will
move packets between SDRAM and Ethernet controller through DMA mechanism. Thus, it could offload the CPU loading and
get better performance. Besides, it also supports full-duplex operation, making possible 200Mbps bandwidth at no additional
cost.
Ethernet 0 Register Set (LAN PORT)
Virtual Address Size (byte) Name
Description
0xBD20_0000 4
ETH0_CNR1 Control register 1
0xBD20_0004 6
ETH0_ID
NIC ID
0xBD20_000C 8
ETH0_MAR Multicast register
0xBD20_0014 4
ETH0_TSAD Transmit Starting Logic Address of
Descriptor
0xBD20_0018 4
ETH0_RSAD Receive Starting Logic Address of
Descriptor
0xBD20_0020 2
ETH0_IMR Ethernet0 Interrupt Mask Register
0xBD20_0024 2
ETH0_ISR
Ethernet0 Interrupt Status Register
0xBD20_0028 4
ETH0_TMF0 Type match filter 0 register
0xBD20_002C 4
ETH0_TMF1 Type match filter 1 register
0xBD20_0030 4
ETH0_TMF2 Type match filter 2 register
0xBD20_0034 4
ETH0_TMF3 Type match filter 3 register
0xBD20_0038 4
ETH0_MII
MII access register
0xBD20_003C 4
ETH0_CNR2 NIC control register 2
0xBD20_0040 16
ETH0_UAR Unicast address filter register
0xBD20_0080 3
ETH0_MPC Indicates the number of packets
discarded due to rx FIFO overflow.
It is a 24-bit counter. It is cleared to
zero by read command.
0xBD20_0084 2
ETH0_TXCOL Transmit collision counter. This
16-bit counter increments by 1 for
every collision event. It rolls over
when becomes full. It is cleared to
zero by read command.
0xBD20_0088 2
ETH0_RXER Receive error count. This 16-bit
counter increments by 1 for each
valid packet received . It is cleared
to zero by read command.
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
Ethernet 1 Register Set (WAN PORT)
Virtual Address Size (byte) Name
0xBD30_0000 4
ETH1_CNR1
0xBD30_0004 6
ETH1_ID
0xBD30_000C 8
ETH1_MAR
Description
Control register 1
NIC ID
Multicast register
Access
R/W
R/W
R/W
CONFIDENTIAL
21
v1.0

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