74ABT899 查看數據表（PDF） - Philips Electronics

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74ABT899

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

Philips Electronics 

Philips Semiconductors

9-bit dual latch transceiver with 8-bit parity

generator/checker (3-State)

Product specification

74ABT899

PIN CONFIGURATION

ODD/EVEN 1

ERRA 2

LEA 3

A0 4

A1 5

A2 6

A3 7

A4 8

TOP VIEW

A5 9

A6 10

A7 11

APAR 12

OEA 13

GND 14

28 VCC

27 OEB

26 B0

25 B1

24 B2

23 B3

22 B4

21 B5

20 B6

19 B7

18 BPAR

17 LEB

16 SEL

15 ERRB

SA00289

PIN DESCRIPTION

SYMBOL

PIN

NUMBER

NAME AND FUNCTION

A0 - A7

4, 5, 6, 7,

8, 9, 10, Latched A bus 3-State inputs/outputs

11

B0 - B7

19, 20,

21, 22,

23, 24,

25, 26

Latched B bus 3-State inputs/outputs

APAR

12

A bus parity 3-State input

BPAR

18

B bus parity 3-State input

ODD/

EVEN

1

Parity select input (Low for EVEN

parity)

OEA, OEB

13, 27

Output enable inputs (gate A to B,

B to A)

SEL

16

Mode select input (Low for generate)

LEA, LEB 3, 17 Latch enable inputs (transparent High)

ERRA,

ERRB

2, 15 Error signal outputs (active-Low)

GND

14

Ground (0V)

VCC

28

Positive supply voltage

PLCC PIN CONFIGURATION

B1 B2 B3 B4 B5 B6 B7

25 24 23 22 21 20 19

B0 26

OEB 27

VCC 28

ODD/

EVEN

1

ERRA 2

LEA 3

A0 4

18 BPAR

17 LEB

16 SEL

15 ERRB

14 GND

13 OEA

12 APAR

5 6 7 8 9 10 11

A1 A2 A3 A4 A5 A6 A7

LOGIC SYMBOL

SA00291

4 5 6 7 8 9 10 11 12

A0 A1 A2 A3 A4 A5 A6 A7 APAR

3

LEA

17

LEB

16

SEL

1

ODD/EVEN

27

OEB

ERRA

2

ERRB

15

13

OEA

B0 B1 B2 B3 B4 B5 B6 B7 BPAR

26 25 24 23 22 21 20 19 18

SA00290

1998 Jan 16

3

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