SAA4952WP 查看數據表（PDF） - Philips Electronics

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SAA4952WP

Memory controller

Philips Electronics 

Philips Semiconductors

Memory controller

Objective specification

SAA4952WP

Table 2 Horizontal display related pulses

ADDRESS

(HEX)

48

49

4A

4B

4C

4D

56

57

4E

4F

64

65

66

67

REGISTER

FUNCTION

BLNDSTA

BLNDSTO

HWE2STA

HWE2STO

HRESTA

HRESTO

HDSTA

HDSTO

HDMSB

HDDEL

HVSP1

HVSP2

HVSP3

HVSP4

start of horizontal blanking pulse (lower 8 of 9 bits)

stop of horizontal blanking pulse (lower 8 of 9 bits)

start of horizontal write enable 2 (lower 8 of 9 bits)

stop of horizontal write enable 2 (lower 8 of 9 bits)

start of horizontal read enable (lower 8 of 9 bits)

stop of horizontal read enable (lower 8 of 9 bits)

start of horizontal display signal HD (lower 8 of 9 bits)

stop of horizontal display signal HD (lower 8 of 9 bits)

bit 0: MSB of BLNDSTA

bit 1: MSB of BLNDSTO

bit 2: MSB of HWE2STA

bit 3: MSB of HWE2STO

bit 4: MSB of HRESTA

bit 5: MSB of HRESTO

bit 6: MSB of HDSTA

bit 7: MSB of HDSTO

bit 0: fine delay of BLND (LSB)

bit 1: fine delay of BLND (MSB)

bit 2: fine delay of HWE2 (LSB)

bit 3: fine delay of HWE2 (MSB)

bit 4: fine delay of HRE (LSB)

bit 5: fine delay of HRE (MSB)

bit 6: fine delay of HD (LSB)

bit 7: fine delay of HD (MSB)

horizontal pulse 1 for frame synchronization, 8-bit resolution

horizontal pulse 2 for frame synchronization, 8-bit resolution

horizontal pulse 3 for frame synchronization, 8-bit resolution

horizontal pulse 4 for frame synchronization, 8-bit resolution

1997 Jun 10

9

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