SAA7188A 查看數據表（PDF） - Philips Electronics
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SAA7188A Datasheet PDF : 36 Pages
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Philips Semiconductors
Digital Video Encoder (DENC2-M)
Preliminary specification
SAA7188A
FUNCTIONAL DESCRIPTION
The digital MPEG-compatible video encoder (DENC2-M)
encodes digital luminance and chrominance into analog
CVBS and simultaneously S-Video (Y/C) signals. NTSC-M
and PAL B/G standards also sub-standards are supported.
The basic encoder function consists of subcarrier
generation and colour modulation also insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements RS-170-A and CCIR 624.
For ease of analog post filtering the signals are twice
oversampled with respect to pixel clock before
digital-to-analog conversion.
For total filter transfer characteristics see Figs 3 to 6. The
DACs are realized with full 10-bit resolution. The encoder
provides three 8-bit wide data ports, that serve different
applications.
The MPEG Port (MP) and the Video Port (VP) accept
8 lines multiplexed Cb-Y-Cr data.
The Video Port (VP) is also able to handle DIG-TV2 family
compatible 16-bit YUV signals. In this event, the Data Port
(DP) is used for the U/V components.
The Data Port can alternatively handle the data of an 8-bit
wide microprocessor interface.
The 8-bit multiplexed Cb-Y-Cr formats are CCIR 656
(D1 format) compatible, but the SAV, EAV etc. codes are
not decoded.
A crystal-stable master clock (LLC) of 27 MHz, which is
twice the CCIR line-locked pixel clock of 13.5 MHz, needs
to be supplied externally. Optionally, a crystal oscillator
input/output pair of pins and an on-chip clock driver is
provided. Additionally, a DMSD2 compatible clock
interface, using CREF (input or output) and RTC (see
“data sheet SAA7151B” ) is available.
The DENC2-M synthesizes all necessary internal signals,
colour subcarrier frequency, and synchronization signals,
from that clock. DENC2-M is always timing master for the
MPEG Port (MP), but it can additionally be configured as
master or slave for the Video Port (VP).
The IC also contains Closed Caption and Extended Data
Services Encoding (Line 21) and supports Anti-Taping
signal generation in accordance with Macrovision; it also
supports OSD via KEY and three-bit overlay techniques by
a 24 × 8 LUT.
The IC can be programmed via I2C-bus or 8-bit MPU
interface, but only one interface configuration can be
active at a time; if the 16-bit Video Port mode (VP and DP)
is being used, only the I2C-bus interface can be selected.
A number of possibilities are provided for setting of
different video parameters such as:
Black and blanking level control
Colour subcarrier frequency
Variable burst amplitude etc.
During reset (RESET = LOW) and after reset is released,
all digital I/O stages are set to input mode. A reset forces
the control interfaces to abort any running bus transfer and
to set register 3AH to contents 13H, register 61H to
contents 15H, and register 6CH to contents 00H. All other
control registers are not influenced by a reset.
Data manager
In the data manager, real time arbitration on the data
stream to be encoded is performed.
Depending on hardware conditions (signals on pins
SEL_ED, KEY, OSD2 to OSD0, MP7 to to MP0,
VP7 to VP0 and DP7 to DP0) and different software
programming either data from the MP port, from the
VP port, or from the OSD port are selected to be encoded
to CVBS and Y/C signals.
Optionally, the OSD colour look-up tables located in this
block, can be read out in a pre-defined sequence (8 steps
per active video line), achieving e.g. a colour bar test
pattern generator without need for an external data
source. The colour bar function is only under software
control.
1996 Jul 08
7
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