Q67121-C1061 查看數據表（PDF） - Siemens AG
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Q67121-C1061 Datasheet PDF : 43 Pages
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1996 Intermediate Version
C161
Pin Definitions and Functions
Symbol
XTAL1
XTAL2
P3.2 –
P3.13
Pin
Input
Number Output
2
I
3
O
5–
I/O
16
I/O
5
I
Function
XTAL1: Input to the oscillator amplifier and input to the internal
clock generator
XTAL2: Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1, while
leaving XTAL2 unconnected. Minimum and maximum high/low
and rise/fall times specified in the AC Characteristics must be
observed.
Port 3 is a 12-bit bidirectional I/O port. It is bit-wise programmable
for input or output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state.
The following Port 3 pins also serve for alternate functions:
P3.2
CAPIN GPT2 Register CAPREL Capture Input
This function is only available on the C161O.
6
O
7
I
8
I
9
I
10
I
11
I/O
12
I/O
13
O
14
I/O
15
O
O
16
I/O
P4.0 – 17-20, I/O
P4.5
23, 24 I/O
17
O
...
...
24
O
RD
25
O
P3.3
T3OUT GPT1 Timer T3 Toggle Latch Output
P3.4
T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input
P3.5
T4IN
GPT1 Timer T4 Input for
Count/Gate/Reload/Capture
P3.6
T3IN
GPT1 Timer T3 Count/Gate Input
P3.7
T2IN
GPT1 Timer T2 Input for
Count/Gate/Reload/Capture
These functions are only available on the C161K and the C161O.
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
MRST
MTSR
TxD0
RxD0
BHE
WRH
SCLK
SSC Master-Rec./Slave-Transmit I/O
SSC Master-Transmit/Slave-Rec. O/I
ASC0 Clock/Data Output (Asyn./Syn.)
ASC0 Data Input (Asyn.) or I/O (Syn.)
Ext. Memory High Byte Enable Signal,
Ext. Memory High Byte Write Strobe
SSC Master Clock Outp./Slave Cl. Inp.
Port 4 is a 6-bit bidirectional I/O port. It is bit-wise programmable
for input or output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state.
In case of an external bus configuration, Port 4 can be used to
output the segment address lines:
P4.0
A16
Least Significant Segment Addr. Line
...
...
...
P4.5
A21
Most Significant Segment Addr. Line
External Memory Read Strobe. RD is activated for every external
instruction or data read access.
Semiconductor Group
4
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