SAF-XC822-1FRA 查看數據表（PDF） - Infineon Technologies

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比赛名单

SAF-XC822-1FRA

8-Bit Single-Chip Microcontroller

Infineon Technologies 

XC822/824

The pin configuration of the XC824 in Figure 5.

General Device Information

P0.6/SPD_0/RXD_1/SDA_0/MTSR_1/

MRST_0/EXINT0_1/T2EX_0/LINE6/TSIN6/

TXD_0/COL2_1/COLA_1

P1.4/EXINT5/COL4/COUT62_0/

COUT63_1

P1.5/CC62_0/COL5/COLA_0

P2.3/CCPOS0_2/CTRAP_2/T2_2/

EXINT3/AN3

P2.2/CCPOS2_1/T12HR_3/T13HR_3/

SCK_1/T1_1/EXINT2/AN2

P2.1/CCPOS1_1/RXD_3/MTSR_4/T0_1/

EXINT1_1/AN1

P2.0/CCPOS0_1/T12HR_2/T13HR_2/

T2EX_3/T2_1/EXINT0_3/AN0

P1.0/SPD_1/RXD_2/T2EX_2/EXINT0_2/

COL0_0/COUT60_0/TXD_1

P1.1/CC60_0/COL1_0/TXD_2

P1.2/EXINT4/COL2_0/COUT61_0/

COUT63_0

1

20

2

19

3

18

4

17

5

16

XC824

6

15

7

14

8

13

9

12

10

11

P0.5/RXD_0/RTCCLK/MTSR_0/MRST_1/

EXINT0_0/LINE5/TSIN5/COUT62_1/TXD_3/

COL1_1/EXF2_2

P0.4/T2EX_1/SCL_0/SCK_0/EXINT1_0/

CTRAP_1/LINE4/TSIN4/EXF2_0/COL0_1/

COL3_1/COLA_2

P0.3/CC60_1/SDA_1/CTRAP_0/

LINE3/TSIN3

P0.2/T1_0/CC62_1/SCL_1/CCPOS2_0/

LINE2/TSIN2

P0.1/T0_0/CC61_1/MTSR_3/MRST_2/

T13HR_0/CCPOS1_0/LINE1/TSIN1

P0.0/T2_0/T13HR_1/MTSR_2/MRST_3/

T12HR_0/CCPOS0_0/LINE0/TSIN0/COUT61_1

VDDC

VSSP

VDDP

P1.3/CC61_0/COL3_0/CC61_0/EXF2_1

Figure 5 XC824 Pin Configuration, PG-DSO-20 Package (top view)

Data Sheet

8

V1.2, 2011-10

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